From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Date: Tue, 06 May 2014 06:57:51 +0000 Subject: Re: [PATCH V4] POWERPC: BOOK3S: KVM: Use the saved dar value and generic make_dsisr Message-Id: <536887EF.2070201@suse.de> List-Id: References: <1399224075-18041-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> <536773C2.1070502@suse.de> <20140506004133.GA12595@iris.ozlabs.ibm.com> In-Reply-To: <20140506004133.GA12595@iris.ozlabs.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org, "Aneesh Kumar K.V" , kvm-ppc@vger.kernel.org, kvm@vger.kernel.org On 06.05.14 02:41, Paul Mackerras wrote: > On Mon, May 05, 2014 at 01:19:30PM +0200, Alexander Graf wrote: >> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote: >>> +#ifdef CONFIG_PPC_BOOK3S_64 >>> + return vcpu->arch.fault_dar; >> How about PA6T and G5s? > G5 sets DAR on an alignment interrupt. > > As for PA6T, I don't know for sure, but if it doesn't, ordinary > alignment interrupts wouldn't be handled properly, since the code in > arch/powerpc/kernel/align.c assumes DAR contains the address being > accessed on all PowerPC CPUs. Now that's a good point. If we simply behave like Linux, I'm fine. This definitely deserves a comment on the #ifdef in the code. Alex From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx2.suse.de (cantor2.suse.de [195.135.220.15]) (using TLSv1 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45ADB141321 for ; Tue, 6 May 2014 16:57:55 +1000 (EST) Message-ID: <536887EF.2070201@suse.de> Date: Tue, 06 May 2014 08:57:51 +0200 From: Alexander Graf MIME-Version: 1.0 To: Paul Mackerras Subject: Re: [PATCH V4] POWERPC: BOOK3S: KVM: Use the saved dar value and generic make_dsisr References: <1399224075-18041-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> <536773C2.1070502@suse.de> <20140506004133.GA12595@iris.ozlabs.ibm.com> In-Reply-To: <20140506004133.GA12595@iris.ozlabs.ibm.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Cc: linuxppc-dev@lists.ozlabs.org, "Aneesh Kumar K.V" , kvm-ppc@vger.kernel.org, kvm@vger.kernel.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On 06.05.14 02:41, Paul Mackerras wrote: > On Mon, May 05, 2014 at 01:19:30PM +0200, Alexander Graf wrote: >> On 05/04/2014 07:21 PM, Aneesh Kumar K.V wrote: >>> +#ifdef CONFIG_PPC_BOOK3S_64 >>> + return vcpu->arch.fault_dar; >> How about PA6T and G5s? > G5 sets DAR on an alignment interrupt. > > As for PA6T, I don't know for sure, but if it doesn't, ordinary > alignment interrupts wouldn't be handled properly, since the code in > arch/powerpc/kernel/align.c assumes DAR contains the address being > accessed on all PowerPC CPUs. Now that's a good point. If we simply behave like Linux, I'm fine. This definitely deserves a comment on the #ifdef in the code. Alex From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Subject: Re: [PATCH V4] POWERPC: BOOK3S: KVM: Use the saved dar value and generic make_dsisr Date: Tue, 06 May 2014 08:57:51 +0200 Message-ID: <536887EF.2070201@suse.de> References: <1399224075-18041-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> <536773C2.1070502@suse.de> <20140506004133.GA12595@iris.ozlabs.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Cc: linuxppc-dev@lists.ozlabs.org, "Aneesh Kumar K.V" , kvm-ppc@vger.kernel.org, kvm@vger.kernel.org To: Paul Mackerras Return-path: In-Reply-To: <20140506004133.GA12595@iris.ozlabs.ibm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+glppd-linuxppc64-dev=m.gmane.org@lists.ozlabs.org Sender: "Linuxppc-dev" List-Id: kvm.vger.kernel.org Ck9uIDA2LjA1LjE0IDAyOjQxLCBQYXVsIE1hY2tlcnJhcyB3cm90ZToKPiBPbiBNb24sIE1heSAw NSwgMjAxNCBhdCAwMToxOTozMFBNICswMjAwLCBBbGV4YW5kZXIgR3JhZiB3cm90ZToKPj4gT24g MDUvMDQvMjAxNCAwNzoyMSBQTSwgQW5lZXNoIEt1bWFyIEsuViB3cm90ZToKPj4+ICsjaWZkZWYg Q09ORklHX1BQQ19CT09LM1NfNjQKPj4+ICsJcmV0dXJuIHZjcHUtPmFyY2guZmF1bHRfZGFyOwo+ PiBIb3cgYWJvdXQgUEE2VCBhbmQgRzVzPwo+IEc1IHNldHMgREFSIG9uIGFuIGFsaWdubWVudCBp bnRlcnJ1cHQuCj4KPiBBcyBmb3IgUEE2VCwgSSBkb24ndCBrbm93IGZvciBzdXJlLCBidXQgaWYg aXQgZG9lc24ndCwgb3JkaW5hcnkKPiBhbGlnbm1lbnQgaW50ZXJydXB0cyB3b3VsZG4ndCBiZSBo YW5kbGVkIHByb3Blcmx5LCBzaW5jZSB0aGUgY29kZSBpbgo+IGFyY2gvcG93ZXJwYy9rZXJuZWwv YWxpZ24uYyBhc3N1bWVzIERBUiBjb250YWlucyB0aGUgYWRkcmVzcyBiZWluZwo+IGFjY2Vzc2Vk IG9uIGFsbCBQb3dlclBDIENQVXMuCgpOb3cgdGhhdCdzIGEgZ29vZCBwb2ludC4gSWYgd2Ugc2lt cGx5IGJlaGF2ZSBsaWtlIExpbnV4LCBJJ20gZmluZS4gVGhpcyAKZGVmaW5pdGVseSBkZXNlcnZl cyBhIGNvbW1lbnQgb24gdGhlICNpZmRlZiBpbiB0aGUgY29kZS4KCgpBbGV4CgpfX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpMaW51eHBwYy1kZXYgbWFpbGlu ZyBsaXN0CkxpbnV4cHBjLWRldkBsaXN0cy5vemxhYnMub3JnCmh0dHBzOi8vbGlzdHMub3psYWJz Lm9yZy9saXN0aW5mby9saW51eHBwYy1kZXY=