From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39710) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wjl65-0005VE-KD for qemu-devel@nongnu.org; Mon, 12 May 2014 03:56:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wjl5z-0004ZD-GZ for qemu-devel@nongnu.org; Mon, 12 May 2014 03:56:29 -0400 Received: from cantor2.suse.de ([195.135.220.15]:46889 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wjl5z-0004Z2-Av for qemu-devel@nongnu.org; Mon, 12 May 2014 03:56:23 -0400 Message-ID: <53707EA5.1070707@suse.de> Date: Mon, 12 May 2014 09:56:21 +0200 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1399041202-26184-1-git-send-email-pbonzini@redhat.com> <1399041202-26184-4-git-send-email-pbonzini@redhat.com> In-Reply-To: <1399041202-26184-4-git-send-email-pbonzini@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 3/8] target-i386: fix set of registers zeroed on reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org Am 02.05.2014 16:33, schrieb Paolo Bonzini: > BND0-3, BNDCFGU, BNDCFGS, BNDSTATUS were not zeroed on reset, but they > should be (Intel Instruction Set Extensions Programming Reference > 319433-015, pages 9-4 and 9-6). Same for YMM. >=20 > XCR0 should be reset to 1. >=20 > TSC and TSC_RESET were zeroed already by the memset, remove the explici= t > assignments. >=20 > Cc: Andreas F=C3=A4rber > Signed-off-by: Paolo Bonzini Reviewed-by: Andreas F=C3=A4rber In general I'm happy if trivial target-specific tweaks like this can go through someone else's tree. :) Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg