[Qemu-devel] [PATCH 0/2 v2] ppc-e500: Adding pci-pin to irq callback and some cleanup

[Qemu-devel] [PATCH 0/2 v2] ppc-e500: Adding pci-pin to irq callback and some cleanup

[Bharat Bhushan]

First patch is doing some cleanup and second patch adds
PCI-PIN (INT[A-D]) to its interrupt number mapping callback.
This is required to support pci device passthrough using VFIO.

Bharat Bhushan (2):
  ppc-e500: some pci related cleanup
  ppc-e500: implement PCI INTx routing

 hw/pci-host/ppce500.c |   39 ++++++++++++++++++++++++++++++---------
 hw/ppc/e500.c         |   13 ++++++++-----
 2 files changed, 38 insertions(+), 14 deletions(-)

[Qemu-devel] [PATCH 1/2 v2] ppc-e500: some pci related cleanup

[Bharat Bhushan]

 - Use PCI_NUM_PINS rather than hardcoding
 - use "pin" wherever possible

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com>
---
v1->v2:
 - No Change

 hw/pci-host/ppce500.c |   14 +++++++-------
 hw/ppc/e500.c         |   12 +++++++-----
 2 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c
index c80b7cb..f672d5f 100644
--- a/hw/pci-host/ppce500.c
+++ b/hw/pci-host/ppce500.c
@@ -87,7 +87,7 @@ struct PPCE500PCIState {
     struct pci_outbound pob[PPCE500_PCI_NR_POBS];
     struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
     uint32_t gasket_time;
-    qemu_irq irq[4];
+    qemu_irq irq[PCI_NUM_PINS];
     uint32_t first_slot;
     /* mmio maps */
     MemoryRegion container;
@@ -252,26 +252,26 @@ static const MemoryRegionOps e500_pci_reg_ops = {
     .endianness = DEVICE_BIG_ENDIAN,
 };
 
-static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
+static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin)
 {
     int devno = pci_dev->devfn >> 3;
     int ret;
 
-    ret = ppce500_pci_map_irq_slot(devno, irq_num);
+    ret = ppce500_pci_map_irq_slot(devno, pin);
 
     pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
-           pci_dev->devfn, irq_num, ret, devno);
+           pci_dev->devfn, pin, ret, devno);
 
     return ret;
 }
 
-static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
+static void mpc85xx_pci_set_irq(void *opaque, int pin, int level)
 {
     qemu_irq *pic = opaque;
 
-    pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
+    pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level);
 
-    qemu_set_irq(pic[irq_num], level);
+    qemu_set_irq(pic[pin], level);
 }
 
 static const VMStateDescription vmstate_pci_outbound = {
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index f984b3e..2a3b8b1 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -613,7 +613,9 @@ void ppce500_init(QEMUMachineInitArgs *args, PPCE500Params *params)
     target_long initrd_size = 0;
     target_ulong cur_base = 0;
     int i;
-    unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
+    /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
+     * 4 respectively */
+    unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
     qemu_irq **irqs, *mpic;
     DeviceState *dev;
     CPUPPCState *firstenv = NULL;
@@ -715,10 +717,10 @@ void ppce500_init(QEMUMachineInitArgs *args, PPCE500Params *params)
     qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
     qdev_init_nofail(dev);
     s = SYS_BUS_DEVICE(dev);
-    sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]);
-    sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]);
-    sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]);
-    sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]);
+    for (i = 0; i < PCI_NUM_PINS; i++) {
+        sysbus_connect_irq(s, i, mpic[pci_irq_nrs[i]]);
+    }
+
     memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
                                 sysbus_mmio_get_region(s, 0));
 
-- 
1.7.0.4

[Qemu-devel] [PATCH 2/2 v2] ppc-e500: implement PCI INTx routing

[Bharat Bhushan]

This patch adds pci pin to irq_num routing callback.
This callback is called from pci_device_route_intx_to_irq to
find which pci device maps to which irq.
This fix is required for pci-device passthrough using vfio.

Also without this patch we gets below prints

"
  PCI: Bug - unimplemented PCI INTx routing (e500-pcihost)
  qemu-system-ppc64: PCI: Bug - unimplemented PCI INTx routing (e500-pcihost) "

and Legacy interrupt does not work with pci device passthrough.

Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
---
v1->v2:
 - Added qdev interface to pass inq number of PCI PINA
   (We assume irq number will be sequential)

 hw/pci-host/ppce500.c |   25 +++++++++++++++++++++++--
 hw/ppc/e500.c         |    1 +
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c
index f672d5f..5ed59e8 100644
--- a/hw/pci-host/ppce500.c
+++ b/hw/pci-host/ppce500.c
@@ -88,7 +88,9 @@ struct PPCE500PCIState {
     struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
     uint32_t gasket_time;
     qemu_irq irq[PCI_NUM_PINS];
+    uint32_t irq_num[PCI_NUM_PINS];
     uint32_t first_slot;
+    uint32_t first_pin_irq;
     /* mmio maps */
     MemoryRegion container;
     MemoryRegion iomem;
@@ -267,13 +269,26 @@ static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin)
 
 static void mpc85xx_pci_set_irq(void *opaque, int pin, int level)
 {
-    qemu_irq *pic = opaque;
+    PPCE500PCIState *s = opaque;
+    qemu_irq *pic = s->irq;;
 
     pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level);
 
     qemu_set_irq(pic[pin], level);
 }
 
+static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin)
+{
+    PCIINTxRoute route;
+    PPCE500PCIState *s = opaque;
+
+    route.mode = PCI_INTX_ENABLED;
+    route.irq = s->irq_num[pin];
+
+    pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq);
+    return route;
+}
+
 static const VMStateDescription vmstate_pci_outbound = {
     .name = "pci_outbound",
     .version_id = 0,
@@ -352,10 +367,14 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
         sysbus_init_irq(dev, &s->irq[i]);
     }
 
+    for (i = 0; i < PCI_NUM_PINS; i++) {
+        s->irq_num[i] = s->first_pin_irq + i;
+    }
+
     memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN);
 
     b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
-                         mpc85xx_pci_map_irq, s->irq, address_space_mem,
+                         mpc85xx_pci_map_irq, s, address_space_mem,
                          &s->pio, PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);
     h->bus = b;
 
@@ -373,6 +392,7 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
     memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
     sysbus_init_mmio(dev, &s->container);
     sysbus_init_mmio(dev, &s->pio);
+    pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq);
 
     return 0;
 }
@@ -403,6 +423,7 @@ static const TypeInfo e500_host_bridge_info = {
 
 static Property pcihost_properties[] = {
     DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
+    DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 2a3b8b1..853a6bc 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -715,6 +715,7 @@ void ppce500_init(QEMUMachineInitArgs *args, PPCE500Params *params)
     /* PCI */
     dev = qdev_create(NULL, "e500-pcihost");
     qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
+    qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
     qdev_init_nofail(dev);
     s = SYS_BUS_DEVICE(dev);
     for (i = 0; i < PCI_NUM_PINS; i++) {
-- 
1.7.0.4

Re: [Qemu-devel] [PATCH 2/2 v2] ppc-e500: implement PCI INTx routing

[Andreas Färber]

> diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c
> index f672d5f..5ed59e8 100644
> --- a/hw/pci-host/ppce500.c
> +++ b/hw/pci-host/ppce500.c
[...]
> @@ -267,13 +269,26 @@ static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin)
>  
>  static void mpc85xx_pci_set_irq(void *opaque, int pin, int level)
>  {
> -    qemu_irq *pic = opaque;
> +    PPCE500PCIState *s = opaque;
> +    qemu_irq *pic = s->irq;;

Double semicolon.

Regards,
Andreas


-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH 2/2 v2] ppc-e500: implement PCI INTx routing

[Alexander Graf]

On 12.05.14 17:29, Andreas Färber wrote:
>> diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c
>> index f672d5f..5ed59e8 100644
>> --- a/hw/pci-host/ppce500.c
>> +++ b/hw/pci-host/ppce500.c
> [...]
>> @@ -267,13 +269,26 @@ static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin)
>>   
>>   static void mpc85xx_pci_set_irq(void *opaque, int pin, int level)
>>   {
>> -    qemu_irq *pic = opaque;
>> +    PPCE500PCIState *s = opaque;
>> +    qemu_irq *pic = s->irq;;
> Double semicolon.

Thanks, fixed in my tree :).


Alex

Re: [Qemu-devel] [PATCH 0/2 v2] ppc-e500: Adding pci-pin to irq callback and some cleanup

[Alexander Graf]

On 12.05.14 11:45, Bharat Bhushan wrote:
> First patch is doing some cleanup and second patch adds
> PCI-PIN (INT[A-D]) to its interrupt number mapping callback.
> This is required to support pci device passthrough using VFIO.

Thanks, applied to ppc-next.


Alex