From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?ISO-8859-15?Q?Christian_K=F6nig?= Subject: Re: [PATCH] drm/radeon: fix register typo on si Date: Tue, 13 May 2014 14:38:30 +0200 Message-ID: <53721246.8040200@vodafone.de> References: <1399322442-23028-1-git-send-email-alexander.deucher@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1399322442-23028-1-git-send-email-alexander.deucher@amd.com> Sender: stable-owner@vger.kernel.org To: Alex Deucher , dri-devel@lists.freedesktop.org Cc: Alex Deucher , stable@vger.kernel.org List-Id: dri-devel@lists.freedesktop.org Am 05.05.2014 22:40, schrieb Alex Deucher: > Probably a copy paste typo. > > Signed-off-by: Alex Deucher > Cc: stable@vger.kernel.org Added to my 3.15 queue. Christian. > --- > drivers/gpu/drm/radeon/sid.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h > index 683532f..7321283 100644 > --- a/drivers/gpu/drm/radeon/sid.h > +++ b/drivers/gpu/drm/radeon/sid.h > @@ -107,8 +107,8 @@ > #define SPLL_CHG_STATUS (1 << 1) > #define SPLL_CNTL_MODE 0x618 > #define SPLL_SW_DIR_CONTROL (1 << 0) > -# define SPLL_REFCLK_SEL(x) ((x) << 8) > -# define SPLL_REFCLK_SEL_MASK 0xFF00 > +# define SPLL_REFCLK_SEL(x) ((x) << 26) > +# define SPLL_REFCLK_SEL_MASK (3 << 26) > > #define CG_SPLL_SPREAD_SPECTRUM 0x620 > #define SSEN (1 << 0)