From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wei Huang Subject: Re: [RFC v3 2/6] xen/arm: Add save/restore support for ARM GIC V2 Date: Tue, 13 May 2014 09:53:28 -0500 Message-ID: <537231E8.2040304@samsung.com> References: <1399583908-21755-1-git-send-email-w1.huang@samsung.com> <1399583908-21755-3-git-send-email-w1.huang@samsung.com> <536C099C.1090606@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-reply-to: <536C099C.1090606@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Andrew Cooper , xen-devel@lists.xen.org Cc: keir@xen.org, ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com, ian.jackson@eu.citrix.com, julien.grall@linaro.org, tim@xen.org, jaeyong.yoo@samsung.com, jbeulich@suse.com, yjhyun.yoo@samsung.com List-Id: xen-devel@lists.xenproject.org >> + >> +/* Info for hypervisor to manage guests (per-vcpu) >> + * - Based on GICv2 >> + * - Mainly store registers of GICH_* >> + */ >> +struct hvm_arm_gich_v2 >> +{ >> + uint32_t gic_hcr; >> + uint32_t gic_vmcr; >> + uint32_t gic_apr; >> + uint32_t gic_lr[64]; >> + uint64_t event_mask; >> + uint64_t lr_mask; > > This has an odd number of uint32_t. I suspect it will end up with a > different structure size between a 32 and 64 bit build of Xen. > I will add a padding field to make all structures 64-bit aligned. Let me know if this isn't what you want. -Wei