From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46988) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkRyh-00026t-NY for qemu-devel@nongnu.org; Wed, 14 May 2014 01:43:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WkRyd-0002W3-3o for qemu-devel@nongnu.org; Wed, 14 May 2014 01:43:43 -0400 Received: from mail-lb0-x233.google.com ([2a00:1450:4010:c04::233]:45819) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkRyc-0002Vp-S5 for qemu-devel@nongnu.org; Wed, 14 May 2014 01:43:39 -0400 Received: by mail-lb0-f179.google.com with SMTP id c11so1016758lbj.24 for ; Tue, 13 May 2014 22:43:37 -0700 (PDT) Message-ID: <53730287.5010509@gmail.com> Date: Wed, 14 May 2014 09:43:35 +0400 From: Sergey Fedorov MIME-Version: 1.0 References: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> <1399997768-32014-5-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1399997768-32014-5-git-send-email-aggelerf@ethz.ch> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 04/23] target-arm: preserve RAO/WI bits of ARMv7 SCTLR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabian Aggeler , qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, Sergey Fedorov , Svetlana Fedoseeva , peter.maydell@linaro.org On 13.05.2014 20:15, Fabian Aggeler wrote: > From: Svetlana Fedoseeva > > Signed-off-by: Svetlana Fedoseeva > Signed-off-by: Sergey Fedorov > Signed-off-by: Fabian Aggeler > --- > target-arm/helper.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 9c3269f..2b57ad9 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -2083,6 +2083,11 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, > { > ARMCPU *cpu = arm_env_get_cpu(env); > > + if (arm_feature(env, ARM_FEATURE_V7)) { > + value |= SCTLR_XP | SCTLR_U | SCTLR_nTWE | SCTLR_nTWI | SCTLR_L > + | SCTLR_CP15BEN | SCTLR_P; /* These bits are RAO/WI */ Actually, some of these bits are RAO/WI since v6. Also, there are some RAZ/WI bits varying over architecture variants. There is some overview at ARM ARM v7-AP section L.7.4. Maybe it is worth to fix more precisely over supported architecture variants? By the way, this patch could be separated from security extensions support patch set. Thanks, Sergey. > + } > + > env->cp15.c1_sys = value; > /* ??? Lots of these bits are not implemented. */ > /* This may enable/disable the MMU, so do a TLB flush. */