From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:48135)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <serge.fdrv@gmail.com>) id 1WkS80-0004IE-Kw
	for qemu-devel@nongnu.org; Wed, 14 May 2014 01:53:26 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <serge.fdrv@gmail.com>) id 1WkS7u-0005GK-LT
	for qemu-devel@nongnu.org; Wed, 14 May 2014 01:53:20 -0400
Received: from mail-lb0-x233.google.com ([2a00:1450:4010:c04::233]:40877)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <serge.fdrv@gmail.com>) id 1WkS7u-0005GE-Cw
	for qemu-devel@nongnu.org; Wed, 14 May 2014 01:53:14 -0400
Received: by mail-lb0-f179.google.com with SMTP id c11so1035952lbj.38
	for <qemu-devel@nongnu.org>; Tue, 13 May 2014 22:53:13 -0700 (PDT)
Message-ID: <537304C8.1030407@gmail.com>
Date: Wed, 14 May 2014 09:53:12 +0400
From: Sergey Fedorov <serge.fdrv@gmail.com>
MIME-Version: 1.0
References: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch>
	<1399997768-32014-7-git-send-email-aggelerf@ethz.ch>
In-Reply-To: <1399997768-32014-7-git-send-email-aggelerf@ethz.ch>
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH v2 06/23] target-arm: add arm_is_secure()
 function
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Fabian Aggeler <aggelerf@ethz.ch>, qemu-devel@nongnu.org
Cc: edgar.iglesias@gmail.com, Sergey Fedorov <s.fedorov@samsung.com>, peter.maydell@linaro.org

On 13.05.2014 20:15, Fabian Aggeler wrote:
> arm_is_secure() function allows to determine CPU security state
> if the CPU implements Security Extensions.
>
> Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
> ---
>  target-arm/cpu.h | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index a56d3d6..6ea0432 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -640,6 +640,21 @@ static inline int arm_feature(CPUARMState *env, int feature)
>      return (env->features & (1ULL << feature)) != 0;
>  }
>  
> +/* Return true if the processor is in secure state */
> +static inline bool arm_is_secure(CPUARMState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> +    if (arm_feature(env, ARM_FEATURE_SECURITY_EXTENSIONS)) {

I think feature test can be safely avoided here. Without this feature
that should be no way to switch to monitor mode and to access SCR register.

> +        return ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) ||
> +                !(env->cp15.c1_scr & 1);
> +    } else {
> +        return false;
> +    }
> +#else
> +    return false;

That is a good question how to treat user emulation: secure or
non-secure. Perhaps assuming user emulation in secure state may simplify
code in the following patches.

> +#endif
> +}
> +
>  /* Return true if the specified exception level is running in AArch64 state. */
>  static inline bool arm_el_is_aa64(CPUARMState *env, int el)
>  {

Thanks,
Sergey.