diff for duplicates of <5373AE9A.3050008@gmail.com> diff --git a/a/1.txt b/N1/1.txt index fca2084..de5e4bd 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ -On 05/14/2014 06:57 PM, Antoine Ténart wrote: +On 05/14/2014 06:57 PM, Antoine T?nart wrote: > On Wed, May 14, 2014 at 06:11:24PM +0200, Arnd Bergmann wrote: ->> On Wednesday 14 May 2014 17:49:29 Antoine Ténart wrote: +>> On Wednesday 14 May 2014 17:49:29 Antoine T?nart wrote: >>> On Wed, May 14, 2014 at 05:31:24PM +0200, Arnd Bergmann wrote: >>>> Why do you need a custom mask? Is that something you could pass >>>> as the argument in the phy descriptor using #phy-cells=<1>? @@ -28,7 +28,7 @@ have no clue how that PHY really looks like or how it is wired up. I think it is time to sum this up a little bit and help Antoine carry on this patches. -From what I understand from the conversation, we have a single PHY +>From what I understand from the conversation, we have a single PHY register set dealing with both SATA ports available on the SoC. Also, from the name of the PHY bits we assume the PHY may be able to work in different modes than just SATA. And we currently have @@ -41,7 +41,7 @@ LVDS PHY that can be configured to support SATA or PCIe. Both are electrically and bit-level compatible, so they could be internally wired-up with AHCI and PCIe controller. -From a DT point-of-view, we need a way to (a) link each SATA or PCIe +>From a DT point-of-view, we need a way to (a) link each SATA or PCIe port to the PHY, (b) specify the PHY lane to be used, and (c) specify the protocol to be used on that lane. If I got it right, Arnd already mentioned to use the phy-specifier to deal with it: @@ -54,34 +54,34 @@ I can think of then would be: berlin2q.dtsi: -genphy: lvds@ea00ff { +genphy: lvds at ea00ff { compatible = "marvell,berlin-lvds-phy"; reg = <0xea00ff 0x100>; #phy-cells = <2>; }; -sata: sata@ab00ff { +sata: sata at ab00ff { compatible = "ahci-platform"; reg = <0xab00ff 0x100>; - sata0: sata-port@0 { + sata0: sata-port at 0 { reg = <0>; phy = <&genphy 0 MODE_SATA>; status = "disabled"; }; - sata1: sata-port@1 { + sata1: sata-port at 1 { reg = <1>; phy = <&genphy 1 MODE_SATA>; status = "disabled"; }; }; -pcie: pcie@ab01ff { +pcie: pcie at ab01ff { compatible = "marvell,berlin-pcie"; reg = <0xab01ff 0x100>; - pcie0: pcie-port@0 { + pcie0: pcie-port at 0 { reg = <0>; /* set phy on a per-board basis */ /* PCIe x1 on Lane 0 : phy = <&genphy 0 MODE_PCIE>; */ @@ -113,8 +113,3 @@ individual port nodes (I haven't looked up if it already exists, sorry) and announce only enabled port child nodes, right? Sebastian - --- -To unsubscribe from this list: send the line "unsubscribe devicetree" in -the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org -More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index aecf44b..48b7466 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,26 +3,15 @@ "ref\020140514154929.GA8016@kwain\0" "ref\04414637.rKolGB14Rm@wuerfel\0" "ref\020140514165722.GA18495@kwain\0" - "From\0Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" - "Subject\0Re: [PATCH v3 1/6] phy: add a driver for the Berlin SATA PHY\0" + "From\0sebastian.hesselbarth@gmail.com (Sebastian Hesselbarth)\0" + "Subject\0[PATCH v3 1/6] phy: add a driver for the Berlin SATA PHY\0" "Date\0Wed, 14 May 2014 19:57:46 +0200\0" - "To\0Antoine T\303\251nart <antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>" - " Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>\0" - "Cc\0linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" - thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org - zmxu-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - kishon-l0cyMroinI0@public.gmane.org - linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org - jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org - " tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "On 05/14/2014 06:57 PM, Antoine T\303\251nart wrote:\n" + "On 05/14/2014 06:57 PM, Antoine T?nart wrote:\n" "> On Wed, May 14, 2014 at 06:11:24PM +0200, Arnd Bergmann wrote:\n" - ">> On Wednesday 14 May 2014 17:49:29 Antoine T\303\251nart wrote:\n" + ">> On Wednesday 14 May 2014 17:49:29 Antoine T?nart wrote:\n" ">>> On Wed, May 14, 2014 at 05:31:24PM +0200, Arnd Bergmann wrote:\n" ">>>> Why do you need a custom mask? Is that something you could pass\n" ">>>> as the argument in the phy descriptor using #phy-cells=<1>?\n" @@ -50,7 +39,7 @@ "I think it is time to sum this up a little bit and help Antoine carry\n" "on this patches.\n" "\n" - "From what I understand from the conversation, we have a single PHY\n" + ">From what I understand from the conversation, we have a single PHY\n" "register set dealing with both SATA ports available on the SoC.\n" "Also, from the name of the PHY bits we assume the PHY may be able\n" "to work in different modes than just SATA. And we currently have\n" @@ -63,7 +52,7 @@ "electrically and bit-level compatible, so they could be internally\n" "wired-up with AHCI and PCIe controller.\n" "\n" - "From a DT point-of-view, we need a way to (a) link each SATA or PCIe\n" + ">From a DT point-of-view, we need a way to (a) link each SATA or PCIe\n" "port to the PHY, (b) specify the PHY lane to be used, and (c) specify\n" "the protocol to be used on that lane. If I got it right, Arnd already\n" "mentioned to use the phy-specifier to deal with it:\n" @@ -76,34 +65,34 @@ "\n" "berlin2q.dtsi:\n" "\n" - "genphy: lvds@ea00ff {\n" + "genphy: lvds at ea00ff {\n" "\tcompatible = \"marvell,berlin-lvds-phy\";\n" "\treg = <0xea00ff 0x100>;\n" "\t#phy-cells = <2>;\n" "};\n" "\n" - "sata: sata@ab00ff {\n" + "sata: sata at ab00ff {\n" "\tcompatible = \"ahci-platform\";\n" "\treg = <0xab00ff 0x100>;\n" "\t\n" - "\tsata0: sata-port@0 {\n" + "\tsata0: sata-port at 0 {\n" "\t\treg = <0>;\n" "\t\tphy = <&genphy 0 MODE_SATA>;\n" "\t\tstatus = \"disabled\";\n" "\t};\n" "\n" - "\tsata1: sata-port@1 {\n" + "\tsata1: sata-port at 1 {\n" "\t\treg = <1>;\n" "\t\tphy = <&genphy 1 MODE_SATA>;\n" "\t\tstatus = \"disabled\";\n" "\t};\n" "};\n" "\n" - "pcie: pcie@ab01ff {\n" + "pcie: pcie at ab01ff {\n" "\tcompatible = \"marvell,berlin-pcie\";\n" "\treg = <0xab01ff 0x100>;\n" "\n" - "\tpcie0: pcie-port@0 {\n" + "\tpcie0: pcie-port at 0 {\n" "\t\treg = <0>;\n" "\t\t/* set phy on a per-board basis */\n" "\t\t/* PCIe x1 on Lane 0 : phy = <&genphy 0 MODE_PCIE>; */\n" @@ -134,11 +123,6 @@ "individual port nodes (I haven't looked up if it already exists, sorry)\n" "and announce only enabled port child nodes, right?\n" "\n" - "Sebastian\n" - "\n" - "--\n" - "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" - "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" - More majordomo info at http://vger.kernel.org/majordomo-info.html + Sebastian -1c24574ce954d80d409f92a2f6ff0ec5bb9a4aa59d928999ae85e3808f93c010 +0adc573e0ece4a322a435ed0ae638623cdcd1b4dc0bc8f809d37d4b2e7ed9fca
diff --git a/a/1.txt b/N2/1.txt index fca2084..659e696 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -28,7 +28,7 @@ have no clue how that PHY really looks like or how it is wired up. I think it is time to sum this up a little bit and help Antoine carry on this patches. -From what I understand from the conversation, we have a single PHY +>From what I understand from the conversation, we have a single PHY register set dealing with both SATA ports available on the SoC. Also, from the name of the PHY bits we assume the PHY may be able to work in different modes than just SATA. And we currently have @@ -41,7 +41,7 @@ LVDS PHY that can be configured to support SATA or PCIe. Both are electrically and bit-level compatible, so they could be internally wired-up with AHCI and PCIe controller. -From a DT point-of-view, we need a way to (a) link each SATA or PCIe +>From a DT point-of-view, we need a way to (a) link each SATA or PCIe port to the PHY, (b) specify the PHY lane to be used, and (c) specify the protocol to be used on that lane. If I got it right, Arnd already mentioned to use the phy-specifier to deal with it: @@ -113,8 +113,3 @@ individual port nodes (I haven't looked up if it already exists, sorry) and announce only enabled port child nodes, right? Sebastian - --- -To unsubscribe from this list: send the line "unsubscribe devicetree" in -the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org -More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N2/content_digest index aecf44b..b0d9635 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -3,21 +3,21 @@ "ref\020140514154929.GA8016@kwain\0" "ref\04414637.rKolGB14Rm@wuerfel\0" "ref\020140514165722.GA18495@kwain\0" - "From\0Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "From\0Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\0" "Subject\0Re: [PATCH v3 1/6] phy: add a driver for the Berlin SATA PHY\0" "Date\0Wed, 14 May 2014 19:57:46 +0200\0" - "To\0Antoine T\303\251nart <antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>" - " Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>\0" - "Cc\0linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" - thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org - zmxu-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - kishon-l0cyMroinI0@public.gmane.org - linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org - jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org - " tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org\0" + "To\0Antoine T\303\251nart <antoine.tenart@free-electrons.com>" + " Arnd Bergmann <arnd@arndb.de>\0" + "Cc\0linux-arm-kernel@lists.infradead.org" + thomas.petazzoni@free-electrons.com + zmxu@marvell.com + devicetree@vger.kernel.org + linux-kernel@vger.kernel.org + kishon@ti.com + linux-ide@vger.kernel.org + alexandre.belloni@free-electrons.com + jszhang@marvell.com + " tj@kernel.org\0" "\00:1\0" "b\0" "On 05/14/2014 06:57 PM, Antoine T\303\251nart wrote:\n" @@ -50,7 +50,7 @@ "I think it is time to sum this up a little bit and help Antoine carry\n" "on this patches.\n" "\n" - "From what I understand from the conversation, we have a single PHY\n" + ">From what I understand from the conversation, we have a single PHY\n" "register set dealing with both SATA ports available on the SoC.\n" "Also, from the name of the PHY bits we assume the PHY may be able\n" "to work in different modes than just SATA. And we currently have\n" @@ -63,7 +63,7 @@ "electrically and bit-level compatible, so they could be internally\n" "wired-up with AHCI and PCIe controller.\n" "\n" - "From a DT point-of-view, we need a way to (a) link each SATA or PCIe\n" + ">From a DT point-of-view, we need a way to (a) link each SATA or PCIe\n" "port to the PHY, (b) specify the PHY lane to be used, and (c) specify\n" "the protocol to be used on that lane. If I got it right, Arnd already\n" "mentioned to use the phy-specifier to deal with it:\n" @@ -134,11 +134,6 @@ "individual port nodes (I haven't looked up if it already exists, sorry)\n" "and announce only enabled port child nodes, right?\n" "\n" - "Sebastian\n" - "\n" - "--\n" - "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" - "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" - More majordomo info at http://vger.kernel.org/majordomo-info.html + Sebastian -1c24574ce954d80d409f92a2f6ff0ec5bb9a4aa59d928999ae85e3808f93c010 +8b2ceec59b19b743642883cfca673d562b0ddadd409078e6087e1217c31fa790
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