Re: [PATCH v7 1/4] xen/arm: p2m: Clean cache PT when the IOMMU doesn't support coherent walk

[Julien Grall <julien.grall@linaro.org>]

On 05/15/2014 04:20 PM, Ian Campbell wrote:
> On Thu, 2014-05-15 at 15:16 +0100, Julien Grall wrote:
>> Some IOMMU don't suppport coherent PT walk. When the p2m is shared with
>> the CPU, Xen has to make sure the PT changes have reached the memory.
>>
>> Introduce new IOMMU function that will check if the IOMMU feature is enabled
>> for a specified domain.
>>
>> On ARM, the platform can contain multiple IOMMUs. Each of them may not
>> have the same set of feature. The domain parameter will be used to get the
>> set of features for IOMMUs used by this domain.
>>
>> Signed-off-by: Julien Grall <julien.grall@linaro.org>
> 
> Acked-by: Ian Campbell <ian.campbell@citrix.com> for the arm bit.

Thanks!

>> @@ -548,10 +568,12 @@ int p2m_alloc_table(struct domain *d)
>>      /* Clear both first level pages */
>>      p = __map_domain_page(page);
>>      clear_page(p);
>> +    clean_xen_dcache_va_range(p, PAGE_SIZE);
>>      unmap_domain_page(p);
>>  
>>      p = __map_domain_page(page + 1);
>>      clear_page(p);
>> +    clean_xen_dcache_va_range(p, PAGE_SIZE);
> 
> 
> I wonder if we need clear_and_clean_page()?

I though about it but I was too lazy to create one. I will add a helper
if I need to resend this series.

>>  
>> +enum iommu_feature
>> +{
>> +    IOMMU_FEAT_COHERENT_WALK,
>> +    IOMMU_FEAT_count,
> 
> Lowercase?

What do you mean?

Regards,

-- 
Julien Grall