From: "Andreas Färber" <afaerber@suse.de>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [Qemu-devel] [PULL 00/15] KVM patches for 2014-05-13
Date: Thu, 15 May 2014 18:54:46 +0200 [thread overview]
Message-ID: <5374F156.9020608@suse.de> (raw)
In-Reply-To: <1399985844-788-1-git-send-email-pbonzini@redhat.com>
Am 13.05.2014 14:57, schrieb Paolo Bonzini:
> Paolo Bonzini (7):
> kvm: reset state from the CPU's reset method
> kvm: forward INIT signals coming from the chipset
> target-i386: fix set of registers zeroed on reset
> target-i386: preserve FPU and MSR state on INIT
> apic: do not accept SIPI on the bootstrap processor
> cpu: make CPU_INTERRUPT_RESET available on all targets
> pc: port 92 reset requires a low->high transition
You forgot to fill in my Rbs, and somehow the Cc:s were not processed to
detect this earlier.
Also to me a generic cpu_soft_reset() contradicts Peter confirming that
doing this in a specific qemu_irq based way is desired? If the PC is
going to implement the qemu_irq triggered logic, then CPU_FOREACH() can
be done in PC code, and no generalization of interrupt names is needed.
Or do you have any non-x86 work cooking as well?
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
next prev parent reply other threads:[~2014-05-15 16:55 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-13 12:57 [Qemu-devel] [PULL 00/15] KVM patches for 2014-05-13 Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 01/15] target-i386: Remove unused data from local array Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 02/15] kvm: make one_reg helpers available for everyone Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 03/15] pci-assign: Fix a bug when map MSI-X table memory failed Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 04/15] pci-assign: limit # of msix vectors Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 05/15] target-i386: set eflags prior to calling svm_load_seg_cache() in svm_helper.c Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 06/15] target-i386: set eflags and cr0 prior to calling cpu_x86_load_seg_cache() in smm_helper.c Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 07/15] target-i386: set eflags prior to calling cpu_x86_load_seg_cache() in seg_helper.c Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 08/15] target-i386: the x86 CPL is stored in CS.selector - auto update hflags accordingly Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 09/15] kvm: reset state from the CPU's reset method Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 10/15] kvm: forward INIT signals coming from the chipset Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 11/15] target-i386: fix set of registers zeroed on reset Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 12/15] target-i386: preserve FPU and MSR state on INIT Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 13/15] apic: do not accept SIPI on the bootstrap processor Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 14/15] cpu: make CPU_INTERRUPT_RESET available on all targets Paolo Bonzini
2014-05-13 12:57 ` [Qemu-devel] [PULL 15/15] pc: port 92 reset requires a low->high transition Paolo Bonzini
2014-05-15 15:27 ` [Qemu-devel] [PULL 00/15] KVM patches for 2014-05-13 Peter Maydell
2014-05-15 16:54 ` Andreas Färber [this message]
2014-05-15 17:08 ` Paolo Bonzini
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