diff for duplicates of <5376A9D9.3070702@gmail.com> diff --git a/a/1.txt b/N1/1.txt index 0b17117..e8deddf 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -20,7 +20,7 @@ On 14.05.2014 03:11, Thomas Abraham wrote: > Changes since v2: > - Safe operating voltage is not required while switching APLL frequency > since the temporary parent's clock is divided down to keep armclk within -> permissible limits. Thanks to Heiko St√ºbner <heiko@sntech.de> for this +> permissible limits. Thanks to Heiko Stübner <heiko@sntech.de> for this > suggesting this. > - Rob had suggested to use max frequency for each of the divider clock > outputs instead of divider values. But due to certain SoC specific diff --git a/a/content_digest b/N1/content_digest index abc8d24..2f2d93c 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -40,7 +40,7 @@ "> Changes since v2:\n" "> - Safe operating voltage is not required while switching APLL frequency\n" "> since the temporary parent's clock is divided down to keep armclk within\n" - "> permissible limits. Thanks to Heiko St\342\210\232\302\272bner <heiko@sntech.de> for this\n" + "> permissible limits. Thanks to Heiko St\303\274bner <heiko@sntech.de> for this\n" "> suggesting this.\n" "> - Rob had suggested to use max frequency for each of the divider clock\n" "> outputs instead of divider values. But due to certain SoC specific\n" @@ -118,4 +118,4 @@ "> delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c\n" > -07d1fc51b0061dc3c27cd4ecb5727070fc394f68e0b468182c11cbea51f3347c +74f36fb77d2b33bccaf39eb41a96e138f9e4cc8516d1d2a6fc2457665f5acdfa
diff --git a/a/1.txt b/N2/1.txt index 0b17117..65acf04 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -20,7 +20,7 @@ On 14.05.2014 03:11, Thomas Abraham wrote: > Changes since v2: > - Safe operating voltage is not required while switching APLL frequency > since the temporary parent's clock is divided down to keep armclk within -> permissible limits. Thanks to Heiko Stübner <heiko@sntech.de> for this +> permissible limits. Thanks to Heiko St?bner <heiko@sntech.de> for this > suggesting this. > - Rob had suggested to use max frequency for each of the divider clock > outputs instead of divider values. But due to certain SoC specific diff --git a/a/content_digest b/N2/content_digest index abc8d24..d15fd0c 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,21 +1,8 @@ "ref\01400029876-5830-1-git-send-email-thomas.ab@samsung.com\0" - "From\0Tomasz Figa <tomasz.figa@gmail.com>\0" - "Subject\0Re: [PATCH v4 0/8] cpufreq: use cpufreq-cpu0 driver for exynos based platforms\0" + "From\0tomasz.figa@gmail.com (Tomasz Figa)\0" + "Subject\0[PATCH v4 0/8] cpufreq: use cpufreq-cpu0 driver for exynos based platforms\0" "Date\0Sat, 17 May 2014 02:14:17 +0200\0" - "To\0Thomas Abraham <ta.omasab@gmail.com>" - cpufreq@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" - "Cc\0mturquette@linaro.org" - shawn.guo@linaro.org - devicetree@vger.kernel.org - rjw@rjwysocki.net - linux-samsung-soc@vger.kernel.org - kgene.kim@samsung.com - t.figa@samsung.com - l.majewski@samsung.com - viresh.kumar@linaro.org - heiko@sntech.de - " thomas.ab@samsung.com\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Thomas,\n" @@ -40,7 +27,7 @@ "> Changes since v2:\n" "> - Safe operating voltage is not required while switching APLL frequency\n" "> since the temporary parent's clock is divided down to keep armclk within\n" - "> permissible limits. Thanks to Heiko St\342\210\232\302\272bner <heiko@sntech.de> for this\n" + "> permissible limits. Thanks to Heiko St?bner <heiko@sntech.de> for this\n" "> suggesting this.\n" "> - Rob had suggested to use max frequency for each of the divider clock\n" "> outputs instead of divider values. But due to certain SoC specific\n" @@ -118,4 +105,4 @@ "> delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c\n" > -07d1fc51b0061dc3c27cd4ecb5727070fc394f68e0b468182c11cbea51f3347c +093e78e2948c63943614f45755aeb24eaf3542c2b21c192c8a360006ce055fe5
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