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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: Olivier Danet <odanet@caramail.com>, qemu-devel <qemu-devel@nongnu.org>
Cc: Blue Swirl <blauwirbel@gmail.com>, Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] target-sparc has inverse cwp logic for SAVE/RESTORE?
Date: Mon, 19 May 2014 11:56:15 +0100	[thread overview]
Message-ID: <5379E34F.8080208@ilande.co.uk> (raw)
In-Reply-To: <5378DA7A.2070902@caramail.com>

On 18/05/14 17:06, Olivier Danet wrote:

> The problem may be related to the fact that the 32bits SPARCv8 and 64bits SPARCv9 work in opposite directions !
>
> SparcV9 standard, page 360/399 :
> The SPARC-V9 CWP register is incremented during a SAVE instruction and decremented during
> a RESTORE instruction. Although this is the opposite of PSR.CWP’s behavior in SPARC-V8, the
> only software it should affect is a few trap handlers that operate in privileged mode, and that must
> be rewritten for SPARC-V9 anyway. This change will have no effect on nonprivileged software.

Ah I wonder if that could be it? I did try swapping the 
increment/decrement operators around in the helpers, however OpenBIOS 
crashed fairly early on so it's obviously not as simple as that. I 
suspect that because a lot of the code is shared been v8/v9 then there 
are some other assumptions that would need to be corrected for this to 
work :/


ATB,

Mark.

  reply	other threads:[~2014-05-19 10:58 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-18 12:48 [Qemu-devel] target-sparc has inverse cwp logic for SAVE/RESTORE? Mark Cave-Ayland
2014-05-18 16:06 ` Olivier Danet
2014-05-19 10:56   ` Mark Cave-Ayland [this message]
2014-05-24  6:26     ` Blue Swirl

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