From: Sergey Fedorov <serge.fdrv@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
Fabian Aggeler <aggelerf@ethz.ch>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
Christopher Covington <cov@codeaurora.org>,
Svetlana Fedoseeva <s.fedoseeva@samsung.com>
Subject: Re: [Qemu-devel] [PATCH v2 01/23] target-arm: add new CPU feature for Security Extensions
Date: Wed, 21 May 2014 20:47:01 +0400 [thread overview]
Message-ID: <537CD885.8000106@gmail.com> (raw)
In-Reply-To: <CAFEAcA_yq62jCjiPMz+vYUvRBNBiCg-c2tC9AmfAodTOi-bUXQ@mail.gmail.com>
On 21.05.2014 20:41, Peter Maydell wrote:
> If we want to have -kernel boot in NS then yes, the bootloader
> stub is the place that code should go.
>
> The difficulty with -kernel being NS is that some guest kernels
> for some boards may be assuming that they will run in secure state
> and can directly access h/w or registers which aren't accessible
> from NS. I guess we need to implement it and then see if any of our
> guest images stop working...
Then maybe we can extend arm_boot_info structure to deal with this.
Regards,
Sergey Fedorov.
next prev parent reply other threads:[~2014-05-21 16:47 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-13 16:15 [Qemu-devel] [PATCH v2 00/23] target-arm: add Security Extensions for CPUs Fabian Aggeler
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 01/23] target-arm: add new CPU feature for Security Extensions Fabian Aggeler
2014-05-21 14:46 ` Peter Maydell
2014-05-21 16:14 ` Christopher Covington
2014-05-21 16:33 ` Sergey Fedorov
2014-05-21 16:41 ` Peter Maydell
2014-05-21 16:47 ` Sergey Fedorov [this message]
2014-05-21 14:51 ` Peter Maydell
2014-05-22 9:09 ` Aggeler Fabian
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 02/23] target-arm: move SCR into Security Extensions register list Fabian Aggeler
2014-05-14 14:19 ` Greg Bellows
2014-05-15 9:28 ` Aggeler Fabian
2014-05-21 14:57 ` Peter Maydell
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 03/23] target-arm: adjust TTBCR for Security Extension feature Fabian Aggeler
2014-05-21 16:06 ` Peter Maydell
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 04/23] target-arm: preserve RAO/WI bits of ARMv7 SCTLR Fabian Aggeler
2014-05-14 5:43 ` Sergey Fedorov
2014-05-21 16:12 ` Peter Maydell
2014-05-22 8:58 ` Aggeler Fabian
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 05/23] target-arm: add CPU Monitor mode Fabian Aggeler
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 06/23] target-arm: add arm_is_secure() function Fabian Aggeler
2014-05-14 5:53 ` Sergey Fedorov
2014-05-14 14:42 ` Greg Bellows
2014-05-14 18:35 ` Fedorov Sergey
2014-05-14 20:22 ` Greg Bellows
2014-05-14 21:29 ` Peter Maydell
2014-05-14 22:22 ` Greg Bellows
2014-05-15 13:00 ` Aggeler Fabian
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 07/23] target-arm: reject switching to monitor mode from non-secure state Fabian Aggeler
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 08/23] target-arm: adjust arm_current_pl() for Security Extensions Fabian Aggeler
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 09/23] target-arm: add non-secure Translation Block flag Fabian Aggeler
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 10/23] target-arm: implement CPACR register logic Fabian Aggeler
2014-05-14 6:06 ` Sergey Fedorov
2014-05-14 18:39 ` Fedorov Sergey
2014-05-15 14:44 ` Fabian Aggeler
2014-05-15 15:06 ` Sergey Fedorov
2014-05-14 13:09 ` Peter Crosthwaite
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 11/23] target-arm: add NSACR support Fabian Aggeler
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 12/23] target-arm: add SDER definition Fabian Aggeler
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 13/23] target-arm: Split TLB for secure state and EL3 in Aarch64 Fabian Aggeler
2014-05-14 6:15 ` Sergey Fedorov
2014-05-13 16:15 ` [Qemu-devel] [PATCH v2 14/23] target-arm: add banked coprocessor register type and macros Fabian Aggeler
2014-05-14 16:42 ` Greg Bellows
2014-05-15 9:02 ` Aggeler Fabian
2014-05-15 18:42 ` Sergey Fedorov
2014-05-15 19:10 ` Aggeler Fabian
2014-05-16 7:06 ` Sergey Fedorov
2014-05-22 7:41 ` Edgar E. Iglesias
2014-05-22 11:49 ` Aggeler Fabian
2014-05-22 12:18 ` Sergey Fedorov
2014-05-22 12:50 ` Aggeler Fabian
2014-05-22 22:21 ` Greg Bellows
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 15/23] target-arm: Restrict EL3 to Aarch32 state Fabian Aggeler
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 16/23] target-arm: Use arm_current_sctlr to access SCTLR Fabian Aggeler
2014-05-22 7:33 ` Edgar E. Iglesias
2014-05-22 14:56 ` Aggeler Fabian
2014-05-22 21:24 ` Edgar E. Iglesias
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 17/23] target-arm: Use raw_write/raw_read whenever possible Fabian Aggeler
2014-05-14 17:32 ` Greg Bellows
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 18/23] target-arm: Convert banked coprocessor registers Fabian Aggeler
2014-05-14 19:47 ` Greg Bellows
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 19/23] target-arm: maintain common bits of banked CP registers Fabian Aggeler
2014-05-14 21:20 ` Greg Bellows
2014-05-15 13:10 ` Aggeler Fabian
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 20/23] target-arm: add MVBAR support Fabian Aggeler
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 21/23] target-arm: implement SMC instruction Fabian Aggeler
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 22/23] target-arm: implement IRQ/FIQ routing to Monitor mode Fabian Aggeler
2014-05-13 16:16 ` [Qemu-devel] [PATCH v2 23/23] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI Fabian Aggeler
2014-05-15 18:57 ` [Qemu-devel] [PATCH v2 00/23] target-arm: add Security Extensions for CPUs Sergey Fedorov
2014-05-16 6:00 ` Aggeler Fabian
2014-05-16 20:56 ` Greg Bellows
2014-05-20 10:00 ` Aggeler Fabian
2014-05-20 15:43 ` Greg Bellows
2014-05-21 14:04 ` Peter Maydell
2014-05-21 13:55 ` Peter Maydell
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