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From: Richard Henderson <rth@twiddle.net>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Cc: aurelien@aurel32.net, HPENNER@de.ibm.com
Subject: Re: [Qemu-devel] [PATCH 2/2] tcg/optimize: Remember garbage high bits for 32-bit ops
Date: Fri, 23 May 2014 13:01:28 -0700	[thread overview]
Message-ID: <537FA918.9080006@twiddle.net> (raw)
In-Reply-To: <537FA597.3050703@redhat.com>

On 05/23/2014 12:46 PM, Paolo Bonzini wrote:
>> @@ -166,11 +166,18 @@ static void tcg_opt_gen_mov(TCGContext *s, int
>> op_index, TCGArg *gen_args,
>>                              TCGOpcode old_op, TCGArg dst, TCGArg src)
>>  {
>>      TCGOpcode new_op = op_to_mov(old_op);
>> +    tcg_target_ulong mask;
>>
>>      s->gen_opc_buf[op_index] = new_op;
>>
>>      reset_temp(dst);
>> -    temps[dst].mask = temps[src].mask;
>> +    mask = temps[src].mask;
>> +    if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) {
>> +        /* High bits of the destination are now garbage.  */
> 
> Or they are zero on x86_64... perhaps this could be some kind of TCG target hook.

Only if we actually issued a "mov" insn.

If the register allocator decided to adjust its tables instead, we won't issue
an insn, at which point we really do have garbage in the high bits.  I don't
think we should be thinking about the target at all at this point.


r~

      reply	other threads:[~2014-05-23 20:01 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-23 18:57 [Qemu-devel] [PATCH 0/2] tcg/optimize fix for known-zero bits Richard Henderson
2014-05-23 18:57 ` [Qemu-devel] [PATCH 1/2] tcg/optimize: Move updating of gen_opc_buf into tcg_opt_gen_mov* Richard Henderson
2014-05-23 18:57 ` [Qemu-devel] [PATCH 2/2] tcg/optimize: Remember garbage high bits for 32-bit ops Richard Henderson
2014-05-23 19:46   ` Paolo Bonzini
2014-05-23 20:01     ` Richard Henderson [this message]

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