From mboxrd@z Thu Jan 1 00:00:00 1970 From: Olivier MATZ Subject: Re: [PATCH] atomic: clarify use of memory barriers Date: Mon, 26 May 2014 16:20:05 +0200 Message-ID: <53834D95.30309@6wind.com> References: <1400578588-21137-1-git-send-email-olivier.matz@6wind.com> <2601191342CEEE43887BDE71AB9772580EFA776F@IRSMSX105.ger.corp.intel.com> <537F56C3.3060503@6wind.com> <2601191342CEEE43887BDE71AB9772580EFB0A95@IRSMSX105.ger.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit To: "Ananyev, Konstantin" , "dev-VfR2kkLFssw@public.gmane.org" Return-path: In-Reply-To: <2601191342CEEE43887BDE71AB9772580EFB0A95-kPTMFJFq+rEu0RiL9chJVbfspsVTdybXVpNB7YpNyf8@public.gmane.org> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" Hi Konstantin, On 05/26/2014 03:57 PM, Ananyev, Konstantin wrote: > In most cases just a compiler barrier is enough, but there are few exceptions. > Always using fence instructions - means introduce unnecessary slowdown for cases, when order is guaranteed. > No using fences in cases, when they are needed - means introduce race window and possible data corruption. > That's why right now people can use either rte_compiler_barrier() or mb/rmb/wmb - whatever is appropriate for particular case. OK, so let's drop this patch for now. Thank you for reviewing and commenting. Regards, Olivier