[Qemu-trivial] DBGAUTHSTATUS register

[Aleksandar Ristovski <aristovski@qnx.com>]

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Hello,


This is not a big issue: DBGAUTHSTATUS, according to the docs, should 
exist. According to "ARM Architecture Reference Manual, ARMv7-A and 
ARMv7-R edition" (DDI0406C_b_arm_architecture_reference_manual.pdf), 
DBGAUTHSTATUS is required in all implementations. Reading it should be 
permitted, even if as RAZ only (implying no features are 
implemented/enabled).

This trivial patch defines cp14 register DBGAUTHSTATUS.


Thank you,

---
Aleksandar Ristovski
QNX Software Systems



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From 88e2c564e8a17c0494024d773db4b6c4a0646342 Mon Sep 17 00:00:00 2001
From: Aleksandar Ristovski <ARistovski@qnx.com>
Date: Thu, 29 May 2014 13:20:45 -0400
Subject: [PATCH] Author: Aleksandar Ristovski <ARistovski@qnx.com> Date:   Thu
 May 29 13:03:28 2014 -0400

    * target-arm/helper.c: Define DBGAUTHSTATUS register as RAZ.
---
 target-arm/helper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index ec031f5..ce1f0aa 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -395,6 +395,8 @@ static const ARMCPRegInfo cp_reginfo[] = {
      */
     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "DBGAUTHSTATUS", .cp = 14, .crn = 7, .crm = 14, .opc1 = 0,
+      .opc2 = 6, .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
-- 
1.9.1