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Date: Mon, 2 Jun 2014 10:49:16 +0100
From: Leon Alrae <leon.alrae@imgtec.com>
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Subject: Re: [Qemu-devel] [PATCH 01/21] target-mips: introduce MIPS64R6 ISA
 and a new generic CPU
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To: Aurelien Jarno <aurelien@aurel32.net>
Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, qemu-devel@nongnu.org

On 30/05/14 17:43, Aurelien Jarno wrote:

>> +        /* A generic CPU providing MIPS64 Release 6 features.
>> +           FIXME: Eventually this should be replaced by a real CPU model. */
>> +        .name = "MIPS64R6-generic",
>> +        .CP0_PRid = 0x00010000,
>> +        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
>> +                       (MMU_TYPE_R4000 << CP0C0_MT),
>> +        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
>> +                       (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
>> +                       (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
>> +                       (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
> 
> Do we really suppport watch registers or EJTAG in QEMU?
> 

EJTAG seems to be supported to some extent (I haven't tested it though).
Therefore I left it available if someone would like to experiment with it.
As far as Watch is concerned, it doesn't seem to be functional, but the
Watch* registers are available. For me it was enough to leave the
feature available in the CPU configuration.

Please let me know if in your opinion these features should be disabled.

Thanks,
Leon