From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52501) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ws3SJ-0006DU-Pu for qemu-devel@nongnu.org; Wed, 04 Jun 2014 01:09:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ws3SB-0005bq-Cv for qemu-devel@nongnu.org; Wed, 04 Jun 2014 01:09:43 -0400 Received: from mail-pb0-f50.google.com ([209.85.160.50]:39565) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ws3SB-0005aa-7p for qemu-devel@nongnu.org; Wed, 04 Jun 2014 01:09:35 -0400 Received: by mail-pb0-f50.google.com with SMTP id ma3so6449109pbc.37 for ; Tue, 03 Jun 2014 22:09:33 -0700 (PDT) Message-ID: <538EAA09.1040105@ozlabs.ru> Date: Wed, 04 Jun 2014 15:09:29 +1000 From: Alexey Kardashevskiy MIME-Version: 1.0 References: <1401787684-31895-1-git-send-email-aik@ozlabs.ru> <1401787684-31895-5-git-send-email-aik@ozlabs.ru> <538DF896.3060904@gmail.com> In-Reply-To: <538DF896.3060904@gmail.com> Content-Type: text/plain; charset=KOI8-R Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 04/29] target-ppc: Copy and split gen_spr_7xx() for 970 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tom Musta , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Alexander Graf On 06/04/2014 02:32 AM, Tom Musta wrote: > On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote: >> +static void gen_spr_book3s_pmu_user(CPUPPCState *env) >> +{ >> + spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", >> + &spr_read_ureg, SPR_NOACCESS, >> + &spr_read_ureg, SPR_NOACCESS, >> + 0x00000000); >> + spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", >> + &spr_read_ureg, SPR_NOACCESS, >> + &spr_read_ureg, SPR_NOACCESS, >> + 0x00000000); >> + spr_register(env, SPR_POWER_UPMC1, "UPMC1", >> + &spr_read_ureg, SPR_NOACCESS, >> + &spr_read_ureg, SPR_NOACCESS, >> + 0x00000000); >> + spr_register(env, SPR_POWER_UPMC2, "UPMC2", >> + &spr_read_ureg, SPR_NOACCESS, >> + &spr_read_ureg, SPR_NOACCESS, >> + 0x00000000); >> + spr_register(env, SPR_POWER_UPMC3, "UPMC3", >> + &spr_read_ureg, SPR_NOACCESS, >> + &spr_read_ureg, SPR_NOACCESS, >> + 0x00000000); >> + spr_register(env, SPR_POWER_UPMC4, "UPMC4", >> + &spr_read_ureg, SPR_NOACCESS, >> + &spr_read_ureg, SPR_NOACCESS, >> + 0x00000000); >> + spr_register(env, SPR_POWER_USIAR, "USIAR", >> + &spr_read_ureg, SPR_NOACCESS, >> + &spr_read_ureg, SPR_NOACCESS, >> + 0x00000000); >> +} > > The Uxxxx regs are writeable from supervisor state, aren't they? (similar comment as UCTRL). Yes, they are. Will fix it. However I did not understand the "similar comment as UCTRL" comment. UCTRL is not writable at all. > There is also this complicating factor in ISA 2.07 (P8) whereby the PMU Uxxxx SPRs are > readable/writeable based on the state of MMCR0[PMCC] (ick!). I'll enable writes to Uxxxx for supermode in v5 of this patch. > I think either of these can be handled in follow up patches. I am also not sure that I see a > compelling reason to model the MMCR0[PMCC] accessibility unless we actually start modeling the > PMU (hard). > > Reviewed-by: Tom Musta > -- Alexey