From: Richard Henderson <rth@twiddle.net>
To: Alexander Graf <agraf@suse.de>, qemu-ppc@nongnu.org
Cc: Tom Musta <tommusta@gmail.com>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 2/2] PPC: e500: Merge 32 and 64 bit SPE emulation
Date: Wed, 04 Jun 2014 14:38:25 -0700 [thread overview]
Message-ID: <538F91D1.1030604@twiddle.net> (raw)
In-Reply-To: <1401916152-27169-2-git-send-email-agraf@suse.de>
On 06/04/2014 02:09 PM, Alexander Graf wrote:
> @@ -9030,13 +8820,10 @@ static inline void gen_evmwumi(DisasContext *ctx)
> t1 = tcg_temp_new_i64();
>
> /* t0 := rA; t1 := rB */
> -#if defined(TARGET_PPC64)
> - tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
> - tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
> -#else
> tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_ext32u_i64(t0, t0);
Better in one step:
tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
> @@ -9112,13 +8899,10 @@ static inline void gen_evmwsmi(DisasContext *ctx)
> t1 = tcg_temp_new_i64();
>
> /* t0 := rA; t1 := rB */
> + tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
> + tcg_gen_ext32s_i64(t0, t0);
> + tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
> + tcg_gen_ext32s_i64(t1, t1);
Similarly.
Although I do wonder about using the actual 32-bit widening multiply
primitives: tcg_gen_mulu2_i32 / tcg_gen_muls2_i32.
I suspect the optimizer would clean up the unsigned version, but it hasn't got
a chance with the signed version.
Otherwise, it looks ok.
r~
next prev parent reply other threads:[~2014-06-04 21:39 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-04 21:09 [Qemu-devel] [PATCH 1/2] TCG: Fix tcg_gen_extr_i64_tl for 32bit Alexander Graf
2014-06-04 21:09 ` [Qemu-devel] [PATCH 2/2] PPC: e500: Merge 32 and 64 bit SPE emulation Alexander Graf
2014-06-04 21:38 ` Richard Henderson [this message]
2014-06-04 21:51 ` Alexander Graf
2014-06-04 21:57 ` Richard Henderson
2014-06-04 21:12 ` [Qemu-devel] [PATCH 1/2] TCG: Fix tcg_gen_extr_i64_tl for 32bit Richard Henderson
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