Re: [PATCH 17/20] perf tools: Support to show SSP register

["Mi, Dapeng" <dapeng1.mi@linux.intel.com>]

On 1/24/2025 12:15 AM, Ian Rogers wrote:
> On Wed, Jan 22, 2025 at 10:21 PM Dapeng Mi <dapeng1.mi@linux.intel.com> wrote:
>> Add SSP register support.
>>
>> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
>> ---
>>  tools/arch/x86/include/uapi/asm/perf_regs.h    | 4 +++-
>>  tools/perf/arch/x86/util/perf_regs.c           | 2 ++
>>  tools/perf/util/intel-pt.c                     | 2 +-
>>  tools/perf/util/perf-regs-arch/perf_regs_x86.c | 2 ++
>>  4 files changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/tools/arch/x86/include/uapi/asm/perf_regs.h b/tools/arch/x86/include/uapi/asm/perf_regs.h
>> index 7c9d2bb3833b..158e353070c3 100644
>> --- a/tools/arch/x86/include/uapi/asm/perf_regs.h
>> +++ b/tools/arch/x86/include/uapi/asm/perf_regs.h
>> @@ -27,9 +27,11 @@ enum perf_event_x86_regs {
>>         PERF_REG_X86_R13,
>>         PERF_REG_X86_R14,
>>         PERF_REG_X86_R15,
>> +       PERF_REG_X86_SSP,
> nit: Would it be worth a comment here? SSP may not be apparent to
> everyone. Perhaps something like:
> ```
> /* Shadow stack pointer (SSP) present on Clearwater Forest and newer models. */

Sure.


> ```
>>         /* These are the limits for the GPRs. */
>>         PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1,
>> -       PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1,
>> +       PERF_REG_X86_64_MAX = PERF_REG_X86_SSP + 1,
>> +       PERF_REG_INTEL_PT_MAX = PERF_REG_X86_R15 + 1,
> nit: It's a little peculiar to me the "+1" here - but that's
> pre-existing. Perhaps comments above here too:
> ```
> /* The MAX_REG_X86_64 used generally, for PEBS, etc. */
> PERF_REG_X86_64_MAX = PERF_REG_X86_SSP + 1,
> /* The MAX_REG_INTEL_PT ignores the SSP register. */
> PERF_REG_INTEL_PT_MAX = PERF_REG_X86_R15 + 1,
> ```
> Otherwise:
> Reviewed-by: Ian Rogers <irogers@google.com>

Sure. Thanks.


>
> Thanks,
> Ian
>
>>         /* These all need two bits set because they are 128bit */
>>         PERF_REG_X86_XMM0  = 32,
>> diff --git a/tools/perf/arch/x86/util/perf_regs.c b/tools/perf/arch/x86/util/perf_regs.c
>> index 12fd93f04802..9f492568f3b4 100644
>> --- a/tools/perf/arch/x86/util/perf_regs.c
>> +++ b/tools/perf/arch/x86/util/perf_regs.c
>> @@ -36,6 +36,8 @@ static const struct sample_reg sample_reg_masks[] = {
>>         SMPL_REG(R14, PERF_REG_X86_R14),
>>         SMPL_REG(R15, PERF_REG_X86_R15),
>>  #endif
>> +       SMPL_REG(SSP, PERF_REG_X86_SSP),
>> +
>>         SMPL_REG2(XMM0, PERF_REG_X86_XMM0),
>>         SMPL_REG2(XMM1, PERF_REG_X86_XMM1),
>>         SMPL_REG2(XMM2, PERF_REG_X86_XMM2),
>> diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c
>> index 30be6dfe09eb..86196275c1e7 100644
>> --- a/tools/perf/util/intel-pt.c
>> +++ b/tools/perf/util/intel-pt.c
>> @@ -2139,7 +2139,7 @@ static u64 *intel_pt_add_gp_regs(struct regs_dump *intr_regs, u64 *pos,
>>         u32 bit;
>>         int i;
>>
>> -       for (i = 0, bit = 1; i < PERF_REG_X86_64_MAX; i++, bit <<= 1) {
>> +       for (i = 0, bit = 1; i < PERF_REG_INTEL_PT_MAX; i++, bit <<= 1) {
>>                 /* Get the PEBS gp_regs array index */
>>                 int n = pebs_gp_regs[i] - 1;
>>
>> diff --git a/tools/perf/util/perf-regs-arch/perf_regs_x86.c b/tools/perf/util/perf-regs-arch/perf_regs_x86.c
>> index 708954a9d35d..9a909f02bc04 100644
>> --- a/tools/perf/util/perf-regs-arch/perf_regs_x86.c
>> +++ b/tools/perf/util/perf-regs-arch/perf_regs_x86.c
>> @@ -54,6 +54,8 @@ const char *__perf_reg_name_x86(int id)
>>                 return "R14";
>>         case PERF_REG_X86_R15:
>>                 return "R15";
>> +       case PERF_REG_X86_SSP:
>> +               return "ssp";
>>
>>  #define XMM(x) \
>>         case PERF_REG_X86_XMM ## x:     \
>> --
>> 2.40.1
>>