From mboxrd@z Thu Jan 1 00:00:00 1970 From: Martyn Welch Subject: Re: Radeon drivers on PowerPC (e500) Date: Wed, 18 Jun 2014 09:09:58 +0100 Message-ID: <53A14956.5030600@ge.com> References: <53A09378.6060101@ge.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: Received: from mx0b-00176a03.pphosted.com (mx0b-00176a03.pphosted.com [67.231.157.48]) by gabe.freedesktop.org (Postfix) with ESMTP id F380D6E3F7 for ; Wed, 18 Jun 2014 04:34:23 -0700 (PDT) Received: from pps.filterd (m0048206.ppops.net [127.0.0.1]) by m0048206.ppops.net-00176a03. (8.14.7/8.14.7) with SMTP id s5I8AAII025231 for ; Wed, 18 Jun 2014 04:10:11 -0400 Received: from alpmlip11.e2k.ad.ge.com (n165-156-000-000.static.ge.com [165.156.5.1] (may be forged)) by m0048206.ppops.net-00176a03. with ESMTP id 1mk69dg5dp-1 (version=TLSv1/SSLv3 cipher=RC4-SHA bits=128 verify=NOT) for ; Wed, 18 Jun 2014 04:10:10 -0400 In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Dave Airlie Cc: Alex Deucher , =?UTF-8?B?Q2hyaXN0aWFuIEvDtm5pZw==?= , dri-devel List-Id: dri-devel@lists.freedesktop.org On 18/06/14 02:05, Dave Airlie wrote: > On 18 June 2014 05:14, Martyn Welch wrote: >> Hi, >> >> I've been asked to try and get a r600 based (E6460) graphics card running on >> a machine powered by a Freescale p4080 (e500 core). I've run into a bit of a >> problem. >> >> I have the driver built into the kernel at this point. When I boot the card >> is detected and it seems to be finding the fimware (I'm also building in the >> required firmware blobs), but I get the following messages: >> >> [drm] Initialized drm 1.1.0 20060810 >> [drm] radeon defaulting to kernel modesetting. >> [drm] radeon kernel modesetting enabled. >> [drm] initializing kernel modesetting (CAICOS 0x1002:0x6763 0x1775:0xC6A7). >> [drm] register mmio base: 0x10000000 >> [drm] register mmio size: 131072 >> ATOM BIOS: GE >> [drm] GPU not posted. posting now... >> radeon 0000:04:00.0: VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF >> (512M used) >> radeon 0000:04:00.0: GTT: 512M 0x0000000020000000 - 0x000000003FFFFFFF >> [drm] Detected VRAM RAM=512M, BAR=256M >> [drm] RAM width 64bits DDR >> [TTM] Zone kernel: Available graphics memory: 338754 kiB >> [TTM] Zone highmem: Available graphics memory: 994110 kiB >> [TTM] Initializing pool allocator >> [TTM] Initializing DMA pool allocator >> [drm] radeon: 512M of VRAM memory ready >> [drm] radeon: 512M of GTT memory ready. >> [drm] Supports vblank timestamp caching Rev 1 (10.10.2010). >> [drm] Driver supports precise vblank timestamp query. >> radeon 0000:04:00.0: radeon: using MSI. >> [drm] radeon: irq initialized. >> [drm] GART: num cpu pages 131072, num gpu pages 131072 >> [drm] probing gen 2 caps for device 111d:808a = 2/0 >> [drm] enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0 >> [drm] Loading CAICOS Microcode >> __ioremap_caller(140000, 4096, 4194304, c02eab20)__ioremap(): phys addr >> 0x140000 is RAM lr ttm_bo_kmap >> radeon 0000:04:00.0: disabling GPU acceleration >> radeon 0000:04:00.0: e957e400 unpin not necessary >> radeon 0000:04:00.0: e957e400 unpin not necessary >> [drm] Radeon Display Connectors >> [drm] Connector 0: >> [drm] DP-1 >> [drm] HPD2 >> [drm] HPD3 >> [drm] DDC: 0x6450 0x6450 0x6454 0x6454 0x6458 0x6458 0x645c 0x645c >> [drm] Encoders: >> [drm] DFP2: INTERNAL_UNIPHY1 >> [drm] Connector 2: >> [drm] DVI-I-1 >> [drm] HPD1 >> [drm] DDC: 0x6430 0x6430 0x6434 0x6434 0x6438 0x6438 0x643c 0x643c >> [drm] Encoders: >> [drm] DFP3: INTERNAL_UNIPHY >> [drm] CRT1: INTERNAL_KLDSCP_DAC1 >> [drm] Internal thermal controller with fan control >> [drm] radeon: power management initialized >> __ioremap_caller(141000, 5242880, 4194304, c02eab20)__ioremap(): phys addr >> 0x141000 is RAM lr ttm_bo_kmap >> [drm:radeonfb_create] *ERROR* failed to create fbcon object -12 >> [drm] Initialized radeon 2.29.0 20080528 for 0000:04:00.0 on minor 0 >> >> There are failed attempts to ioremap RAM, initially as part of >> r600_vram_scratch_init() and again I guess mapping the GART? >> >> On the e500, overlapping TLBs are not allowed and there is an explict check >> in arch/powerpc/mm/pgtable_32.c __ioremap_caller() to protect against >> ioremapping RAM that's already got TLB entries which is resulting in the >> error messages. > > I don't think we ever ioremap GART, it should kmap GART pages, ioremap > should only happen for VRAM areas AFAIK, > Ah, quite possibly, I hadn't looked in any depth further than the initial failure with r600_vram_scratch_init() as that was going to be a bit of a blocker. > This isn't some 32-bit vs 36-bit BAR or something, I seem to remember BenH > mentioning something like that before. > Thanks Dave. Martyn -- Martyn Welch (Lead Software Engineer) | Registered in England and Wales GE Intelligent Platforms | (3828642) at 100 Barbirolli Square T +44(0)1327322748 | Manchester, M2 3AB E martyn.welch@ge.com | VAT:GB 927559189