From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37868) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxHfv-0000fy-6T for qemu-devel@nongnu.org; Wed, 18 Jun 2014 11:21:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WxHfo-0006dI-2v for qemu-devel@nongnu.org; Wed, 18 Jun 2014 11:21:23 -0400 Received: from cantor2.suse.de ([195.135.220.15]:54909 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxHfn-0006dB-P2 for qemu-devel@nongnu.org; Wed, 18 Jun 2014 11:21:16 -0400 Message-ID: <53A1AE69.9060904@suse.de> Date: Wed, 18 Jun 2014 17:21:13 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1401385013-40740-1-git-send-email-petar.jovanovic@rt-rk.com> In-Reply-To: <1401385013-40740-1-git-send-email-petar.jovanovic@rt-rk.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [v4 PATCH] target-mips: implement UserLocal Register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Petar Jovanovic , qemu-devel@nongnu.org Cc: petar.jovanovic@imgtec.com, aurelien@aurel32.net, rth@twiddle.net Am 29.05.2014 19:36, schrieb Petar Jovanovic: > From: Petar Jovanovic >=20 > From MIPS documentation (Volume III): >=20 > UserLocal Register (CP0 Register 4, Select 2) > Compliance Level: Recommended. >=20 > The UserLocal register is a read-write register that is not interpreted= by > the hardware and conditionally readable via the RDHWR instruction. >=20 > This register only exists if the Config3-ULRI register field is set. >=20 > Privileged software may write this register with arbitrary information = and > make it accessible to unprivileged software via register 29 (ULR) of th= e > RDHWR instruction. To do so, bit 29 of the HWREna register must be set = to a > 1 to enable unprivileged access to the register. >=20 > Signed-off-by: Petar Jovanovic > --- > v4: > - removed MIPS_HFLAG_CP0UL, DisasContext now has a field ulri that is u= sed > for the same purpose; >=20 > v3: > - new hflag MIPS_HFLAG_HWRENA_ULR introduced, it is set when ULR bit > from HWREna is set > - helper rdhwr_ul removed, now the checks for rdhwr are done at > translation time > - CPU_SAVE_VERSION switched to 4, load_tc supports both (3 and 4) > version ids >=20 > v2: > - Defined MIPS_HFLAG_CP0UL flag, checks are now based on hflags > - CP0_UserLocal moved to struct TCState > - Added tc->CP0_UserLocal in save_tc/load_tc in target-mips/machine.c > - Reused CP0_UserLocal field for user-mode purpose >=20 > linux-user/mips/target_cpu.h | 2 +- > linux-user/syscall.c | 2 +- > target-mips/cpu.h | 11 +++++---- > target-mips/machine.c | 13 ++++++---- > target-mips/op_helper.c | 14 ++++++++++- > target-mips/translate.c | 54 ++++++++++++++++++++++++++++++++++= +++++--- > 6 files changed, 82 insertions(+), 14 deletions(-) >=20 > diff --git a/linux-user/mips/target_cpu.h b/linux-user/mips/target_cpu.= h > index ba8e9eb..19b8855 100644 > --- a/linux-user/mips/target_cpu.h > +++ b/linux-user/mips/target_cpu.h > @@ -30,7 +30,7 @@ static inline void cpu_clone_regs(CPUMIPSState *env, = target_ulong newsp) > =20 > static inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls) > { > - env->tls_value =3D newtls; > + env->active_tc.CP0_UserLocal =3D newtls; > } > =20 > #endif > diff --git a/linux-user/syscall.c b/linux-user/syscall.c > index 6efeeff..fda8dd6 100644 > --- a/linux-user/syscall.c > +++ b/linux-user/syscall.c > @@ -8686,7 +8686,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_l= ong arg1, > #ifdef TARGET_NR_set_thread_area > case TARGET_NR_set_thread_area: > #if defined(TARGET_MIPS) > - ((CPUMIPSState *) cpu_env)->tls_value =3D arg1; > + ((CPUMIPSState *) cpu_env)->active_tc.CP0_UserLocal =3D arg1; > ret =3D 0; > break; > #elif defined(TARGET_CRIS) > diff --git a/target-mips/cpu.h b/target-mips/cpu.h > index 6c2014e..833e592 100644 > --- a/target-mips/cpu.h > +++ b/target-mips/cpu.h > @@ -167,6 +167,7 @@ struct TCState { > target_ulong CP0_TCSchedule; > target_ulong CP0_TCScheFBack; > int32_t CP0_Debug_tcstatus; > + target_ulong CP0_UserLocal; > }; > =20 > typedef struct CPUMIPSState CPUMIPSState; > @@ -361,6 +362,7 @@ struct CPUMIPSState { > int32_t CP0_Config3; > #define CP0C3_M 31 > #define CP0C3_ISA_ON_EXC 16 > +#define CP0C3_ULRI 13 > #define CP0C3_DSPP 10 > #define CP0C3_LPA 7 > #define CP0C3_VEIC 6 > @@ -469,6 +471,8 @@ struct CPUMIPSState { > /* MIPS DSP resources access. */ > #define MIPS_HFLAG_DSP 0x40000 /* Enable access to MIPS DSP resourc= es. */ > #define MIPS_HFLAG_DSPR2 0x80000 /* Enable access to MIPS DSPR2 resou= rces. */ > + /* Extra flag about HWREna register. */ > +#define MIPS_HFLAG_HWRENA_ULR 0x100000 /* ULR bit from HWREna is set. = */ > target_ulong btarget; /* Jump / branch target = */ > target_ulong bcond; /* Branch condition (if needed) = */ > =20 > @@ -478,8 +482,6 @@ struct CPUMIPSState { > uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStat= us */ > int insn_flags; /* Supported instruction set */ > =20 > - target_ulong tls_value; /* For usermode emulation */ > - > CPU_COMMON > =20 > /* Fields from here on are preserved across CPU reset. */ > @@ -522,7 +524,7 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_f= printf); > extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *en= v); > extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); > =20 > -#define CPU_SAVE_VERSION 3 > +#define CPU_SAVE_VERSION 4 > =20 > /* MMU modes definitions. We carefully match the indices with our > hflags layout. */ > @@ -681,7 +683,8 @@ static inline void cpu_get_tb_cpu_state(CPUMIPSStat= e *env, target_ulong *pc, > { > *pc =3D env->active_tc.PC; > *cs_base =3D 0; > - *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); > + *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | > + MIPS_HFLAG_HWRENA_ULR); > } > =20 > static inline int mips_vpe_active(CPUMIPSState *env) > diff --git a/target-mips/machine.c b/target-mips/machine.c > index 0a07db8..0f36c9e 100644 > --- a/target-mips/machine.c > +++ b/target-mips/machine.c > @@ -25,6 +25,7 @@ static void save_tc(QEMUFile *f, TCState *tc) > qemu_put_betls(f, &tc->CP0_TCSchedule); > qemu_put_betls(f, &tc->CP0_TCScheFBack); > qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus); > + qemu_put_betls(f, &tc->CP0_UserLocal); > } > =20 > static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) > @@ -151,7 +152,7 @@ void cpu_save(QEMUFile *f, void *opaque) > save_fpu(f, &env->fpus[i]); > } > =20 > -static void load_tc(QEMUFile *f, TCState *tc) > +static void load_tc(QEMUFile *f, TCState *tc, int version_id) > { > int i; > =20 > @@ -173,6 +174,9 @@ static void load_tc(QEMUFile *f, TCState *tc) > qemu_get_betls(f, &tc->CP0_TCSchedule); > qemu_get_betls(f, &tc->CP0_TCScheFBack); > qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus); > + if (version_id >=3D 4) { > + qemu_get_betls(f, &tc->CP0_UserLocal); > + } > } > =20 > static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) > @@ -194,11 +198,12 @@ int cpu_load(QEMUFile *f, void *opaque, int versi= on_id) > MIPSCPU *cpu =3D mips_env_get_cpu(env); > int i; > =20 > - if (version_id !=3D 3) > + if (version_id < 3) { > return -EINVAL; > + } > =20 > /* Load active TC */ > - load_tc(f, &env->active_tc); > + load_tc(f, &env->active_tc, version_id); > =20 > /* Load active FPU */ > load_fpu(f, &env->active_fpu); > @@ -299,7 +304,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version= _id) > =20 > /* Load inactive TC state */ > for (i =3D 0; i < MIPS_SHADOW_SET_MAX; i++) > - load_tc(f, &env->tcs[i]); > + load_tc(f, &env->tcs[i], version_id); Since Leon spotted an issue, can you please add braces for this loop while at it? > for (i =3D 0; i < MIPS_FPU_MAX; i++) > load_fpu(f, &env->fpus[i]); > =20 [snip] Load/save and translation code looks good now. Thanks, Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg