From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [qom-cpu PATCH 3/3] target-i386: Don't enable nested VMX by default Date: Thu, 19 Jun 2014 11:23:57 +0200 Message-ID: <53A2AC2D.4040305@redhat.com> References: <1403121359-4275-1-git-send-email-ehabkost@redhat.com> <1403121359-4275-4-git-send-email-ehabkost@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: kvm@vger.kernel.org, Aurelien Jarno , Igor Mammedov , "Michael S. Tsirkin" To: Eduardo Habkost , qemu-devel@nongnu.org, =?ISO-8859-1?Q?Andreas_F=E4rber?= Return-path: Received: from mail-wi0-f170.google.com ([209.85.212.170]:50965 "EHLO mail-wi0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755362AbaFSJYB (ORCPT ); Thu, 19 Jun 2014 05:24:01 -0400 Received: by mail-wi0-f170.google.com with SMTP id cc10so9766923wib.5 for ; Thu, 19 Jun 2014 02:24:00 -0700 (PDT) In-Reply-To: <1403121359-4275-4-git-send-email-ehabkost@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: Il 18/06/2014 21:55, Eduardo Habkost ha scritto: > TCG doesn't support VMX, and nested VMX is not enabled by default on the > KVM kernel module. > > So, there's no reason to have VMX enabled by default on the core2duo and > coreduo CPU models, today. Even the newer Intel CPU model definitions > don't have it enabled. > > In this case, we need machine-type compat code, as people may be running > the older machine-types on hosts that had VMX nesting enabled. > > Signed-off-by: Eduardo Habkost > --- > hw/i386/pc_piix.c | 2 ++ > hw/i386/pc_q35.c | 2 ++ > target-i386/cpu.c | 8 ++++---- > 3 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c > index a48e263..61882d5 100644 > --- a/hw/i386/pc_piix.c > +++ b/hw/i386/pc_piix.c > @@ -267,6 +267,8 @@ static void pc_init_pci(MachineState *machine) > static void pc_compat_2_0(MachineState *machine) > { > smbios_legacy_mode = true; > + x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VMX, 0); > + x86_cpu_compat_set_features("core2duo", FEAT_1_ECX, CPUID_EXT_VMX, 0); > } > > static void pc_compat_1_7(MachineState *machine) > diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c > index b3c02c1..3949267 100644 > --- a/hw/i386/pc_q35.c > +++ b/hw/i386/pc_q35.c > @@ -245,6 +245,8 @@ static void pc_q35_init(MachineState *machine) > static void pc_compat_2_0(MachineState *machine) > { > smbios_legacy_mode = true; > + x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VMX, 0); > + x86_cpu_compat_set_features("core2duo", FEAT_1_ECX, CPUID_EXT_VMX, 0); > } > > static void pc_compat_1_7(MachineState *machine) > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index 2f32d29..6bd44e1 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -719,10 +719,10 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | > CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, > /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, > - * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM */ > + * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ > .features[FEAT_1_ECX] = > CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | > - CPUID_EXT_VMX | CPUID_EXT_CX16, > + CPUID_EXT_CX16, > .features[FEAT_8000_0001_EDX] = > CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, > .features[FEAT_8000_0001_ECX] = > @@ -803,9 +803,9 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | > CPUID_SS, > /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, > - * CPUID_EXT_PDCM */ > + * CPUID_EXT_PDCM, CPUID_EXT_VMX */ > .features[FEAT_1_ECX] = > - CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX, > + CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, > .features[FEAT_8000_0001_EDX] = > CPUID_EXT2_NX, > .xlevel = 0x80000008, > Could you please do the same for SVM, perhaps with the exception of qemu64? Nested SVM is enabled by default upstream, but right now it is probably less stable than nested VMX. Paolo From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45190) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxYZm-0000nt-PB for qemu-devel@nongnu.org; Thu, 19 Jun 2014 05:24:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WxYZd-0004kW-HV for qemu-devel@nongnu.org; Thu, 19 Jun 2014 05:24:10 -0400 Received: from mail-wi0-x232.google.com ([2a00:1450:400c:c05::232]:64784) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxYZd-0004kD-7v for qemu-devel@nongnu.org; Thu, 19 Jun 2014 05:24:01 -0400 Received: by mail-wi0-f178.google.com with SMTP id n15so2490315wiw.5 for ; Thu, 19 Jun 2014 02:24:00 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <53A2AC2D.4040305@redhat.com> Date: Thu, 19 Jun 2014 11:23:57 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1403121359-4275-1-git-send-email-ehabkost@redhat.com> <1403121359-4275-4-git-send-email-ehabkost@redhat.com> In-Reply-To: <1403121359-4275-4-git-send-email-ehabkost@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [qom-cpu PATCH 3/3] target-i386: Don't enable nested VMX by default List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Eduardo Habkost , qemu-devel@nongnu.org, =?ISO-8859-1?Q?Andreas_F=E4rber?= Cc: Igor Mammedov , Aurelien Jarno , kvm@vger.kernel.org, "Michael S. Tsirkin" Il 18/06/2014 21:55, Eduardo Habkost ha scritto: > TCG doesn't support VMX, and nested VMX is not enabled by default on the > KVM kernel module. > > So, there's no reason to have VMX enabled by default on the core2duo and > coreduo CPU models, today. Even the newer Intel CPU model definitions > don't have it enabled. > > In this case, we need machine-type compat code, as people may be running > the older machine-types on hosts that had VMX nesting enabled. > > Signed-off-by: Eduardo Habkost > --- > hw/i386/pc_piix.c | 2 ++ > hw/i386/pc_q35.c | 2 ++ > target-i386/cpu.c | 8 ++++---- > 3 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c > index a48e263..61882d5 100644 > --- a/hw/i386/pc_piix.c > +++ b/hw/i386/pc_piix.c > @@ -267,6 +267,8 @@ static void pc_init_pci(MachineState *machine) > static void pc_compat_2_0(MachineState *machine) > { > smbios_legacy_mode = true; > + x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VMX, 0); > + x86_cpu_compat_set_features("core2duo", FEAT_1_ECX, CPUID_EXT_VMX, 0); > } > > static void pc_compat_1_7(MachineState *machine) > diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c > index b3c02c1..3949267 100644 > --- a/hw/i386/pc_q35.c > +++ b/hw/i386/pc_q35.c > @@ -245,6 +245,8 @@ static void pc_q35_init(MachineState *machine) > static void pc_compat_2_0(MachineState *machine) > { > smbios_legacy_mode = true; > + x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VMX, 0); > + x86_cpu_compat_set_features("core2duo", FEAT_1_ECX, CPUID_EXT_VMX, 0); > } > > static void pc_compat_1_7(MachineState *machine) > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index 2f32d29..6bd44e1 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -719,10 +719,10 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | > CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, > /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, > - * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM */ > + * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ > .features[FEAT_1_ECX] = > CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | > - CPUID_EXT_VMX | CPUID_EXT_CX16, > + CPUID_EXT_CX16, > .features[FEAT_8000_0001_EDX] = > CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, > .features[FEAT_8000_0001_ECX] = > @@ -803,9 +803,9 @@ static X86CPUDefinition builtin_x86_defs[] = { > CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | > CPUID_SS, > /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, > - * CPUID_EXT_PDCM */ > + * CPUID_EXT_PDCM, CPUID_EXT_VMX */ > .features[FEAT_1_ECX] = > - CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX, > + CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, > .features[FEAT_8000_0001_EDX] = > CPUID_EXT2_NX, > .xlevel = 0x80000008, > Could you please do the same for SVM, perhaps with the exception of qemu64? Nested SVM is enabled by default upstream, but right now it is probably less stable than nested VMX. Paolo