diff for duplicates of <53A2C690.1060106@ti.com> diff --git a/a/content_digest b/N1/content_digest index b3d36ad..7fef12d 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -4,15 +4,15 @@ "Subject\0Re: [PATCH v2 10/18] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY\0" "Date\0Thu, 19 Jun 2014 14:16:32 +0300\0" "To\0Kishon Vijay Abraham I <kishon@ti.com>" - devicetree@vger.kernel.org - linux-doc@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-omap@vger.kernel.org - linux-pci@vger.kernel.org - " linux-kernel@vger.kernel.org\0" - "Cc\0arnd@arndb.de" - tony@atomide.com - jg1.han@samsung.com + <devicetree@vger.kernel.org> + <linux-doc@vger.kernel.org> + <linux-arm-kernel@lists.infradead.org> + <linux-omap@vger.kernel.org> + <linux-pci@vger.kernel.org> + " <linux-kernel@vger.kernel.org>\0" + "Cc\0<arnd@arndb.de>" + <tony@atomide.com> + <jg1.han@samsung.com> Rajendra Nayak <rnayak@ti.com> Paul Walmsley <paul@pwsan.com> Rob Herring <robh+dt@kernel.org> @@ -66,4 +66,4 @@ "> \t\tclocks = <&apll_pcie_ck>;\n" > -fe34e149ee9d9128adcc6bd0abec82a71df50c609bd37abd7bbf599f9308b083 +d17113fb6c3aff4105cfbed0223eab35b1e28d066313b2b5e47afc6c65eea9f3
diff --git a/a/1.txt b/N2/1.txt index a31743e..b6a416e 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -30,7 +30,7 @@ about hardware details. Other than that, looks good to me. > reg = <0x021c>, <0x0220>; > }; > -> + optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 { +> + optfclk_pciephy_32khz: optfclk_pciephy_32khz at 4a0093b0 { > + compatible = "ti,gate-clock"; > + clocks = <&sys_32k_ck>; > + #clock-cells = <0>; @@ -38,7 +38,7 @@ about hardware details. Other than that, looks good to me. > + ti,bit-shift = <8>; > + }; > + -> optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { +> optfclk_pciephy_div: optfclk_pciephy_div at 4a00821c { > compatible = "ti,divider-clock"; > clocks = <&apll_pcie_ck>; > diff --git a/a/content_digest b/N2/content_digest index b3d36ad..6ca51af 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,24 +1,9 @@ "ref\01401345500-20188-1-git-send-email-kishon@ti.com\0" "ref\01401345500-20188-11-git-send-email-kishon@ti.com\0" - "From\0Tero Kristo <t-kristo@ti.com>\0" - "Subject\0Re: [PATCH v2 10/18] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY\0" + "From\0t-kristo@ti.com (Tero Kristo)\0" + "Subject\0[PATCH v2 10/18] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY\0" "Date\0Thu, 19 Jun 2014 14:16:32 +0300\0" - "To\0Kishon Vijay Abraham I <kishon@ti.com>" - devicetree@vger.kernel.org - linux-doc@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-omap@vger.kernel.org - linux-pci@vger.kernel.org - " linux-kernel@vger.kernel.org\0" - "Cc\0arnd@arndb.de" - tony@atomide.com - jg1.han@samsung.com - Rajendra Nayak <rnayak@ti.com> - Paul Walmsley <paul@pwsan.com> - Rob Herring <robh+dt@kernel.org> - Pawel Moll <pawel.moll@arm.com> - Mark Rutland <mark.rutland@arm.com> - " Kumar Gala <galak@codeaurora.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:\n" @@ -53,7 +38,7 @@ "> \t\treg = <0x021c>, <0x0220>;\n" "> \t};\n" ">\n" - "> +\toptfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {\n" + "> +\toptfclk_pciephy_32khz: optfclk_pciephy_32khz at 4a0093b0 {\n" "> +\t\tcompatible = \"ti,gate-clock\";\n" "> +\t\tclocks = <&sys_32k_ck>;\n" "> +\t\t#clock-cells = <0>;\n" @@ -61,9 +46,9 @@ "> +\t\tti,bit-shift = <8>;\n" "> +\t};\n" "> +\n" - "> \toptfclk_pciephy_div: optfclk_pciephy_div@4a00821c {\n" + "> \toptfclk_pciephy_div: optfclk_pciephy_div at 4a00821c {\n" "> \t\tcompatible = \"ti,divider-clock\";\n" "> \t\tclocks = <&apll_pcie_ck>;\n" > -fe34e149ee9d9128adcc6bd0abec82a71df50c609bd37abd7bbf599f9308b083 +6dbdfbaa0e3ac6e5424bb3a243849f0744e3c88b708d65839f12e6162c0b0604
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