diff for duplicates of <53A2C787.5060905@ti.com> diff --git a/a/content_digest b/N1/content_digest index 7908ba4..afdf3f8 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -4,15 +4,15 @@ "Subject\0Re: [PATCH v2 13/18] ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance\0" "Date\0Thu, 19 Jun 2014 14:20:39 +0300\0" "To\0Kishon Vijay Abraham I <kishon@ti.com>" - devicetree@vger.kernel.org - linux-doc@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-omap@vger.kernel.org - linux-pci@vger.kernel.org - " linux-kernel@vger.kernel.org\0" - "Cc\0arnd@arndb.de" - tony@atomide.com - jg1.han@samsung.com + <devicetree@vger.kernel.org> + <linux-doc@vger.kernel.org> + <linux-arm-kernel@lists.infradead.org> + <linux-omap@vger.kernel.org> + <linux-pci@vger.kernel.org> + " <linux-kernel@vger.kernel.org>\0" + "Cc\0<arnd@arndb.de>" + <tony@atomide.com> + <jg1.han@samsung.com> Rajendra Nayak <rnayak@ti.com> Paul Walmsley <paul@pwsan.com> Rob Herring <robh+dt@kernel.org> @@ -98,4 +98,4 @@ "> \t\tcompatible = \"fixed-factor-clock\";\n" > -d2f25ea9c69898f2b48aefe5e3466191911bf0e07bbf2a06c9e25dbc73484a6b +e71dfad814b8f7bd36df23cde7741edad909bbdd706c09d40aa09ca6b7d9c6d4
diff --git a/a/1.txt b/N2/1.txt index bc06e99..00f52fc 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -31,7 +31,7 @@ clock layout. Also, is the register offset wrong on these? Should be > ti,bit-shift = <8>; > }; > -> + optfclk_pciephy2_32khz: optfclk_pciephy_32khz@4a0093b4 { +> + optfclk_pciephy2_32khz: optfclk_pciephy_32khz at 4a0093b4 { > + compatible = "ti,gate-clock"; > + clocks = <&sys_32k_ck>; > + #clock-cells = <0>; @@ -39,14 +39,14 @@ clock layout. Also, is the register offset wrong on these? Should be > + ti,bit-shift = <8>; > + }; > + -> optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { +> optfclk_pciephy_div: optfclk_pciephy_div at 4a00821c { > compatible = "ti,divider-clock"; > clocks = <&apll_pcie_ck>; > @@ -1191,6 +1199,14 @@ > ti,bit-shift = <9>; > }; > -> + optfclk_pciephy2_clk: optfclk_pciephy_clk@4a0093b4 { +> + optfclk_pciephy2_clk: optfclk_pciephy_clk at 4a0093b4 { > + compatible = "ti,gate-clock"; > + clocks = <&apll_pcie_ck>; > + #clock-cells = <0>; @@ -54,14 +54,14 @@ clock layout. Also, is the register offset wrong on these? Should be > + ti,bit-shift = <9>; > + }; > + -> optfclk_pciephy1_div_clk: optfclk_pciephy_div_clk@4a0093b0 { +> optfclk_pciephy1_div_clk: optfclk_pciephy_div_clk at 4a0093b0 { > compatible = "ti,gate-clock"; > clocks = <&optfclk_pciephy_div>; > @@ -1199,6 +1215,14 @@ > ti,bit-shift = <10>; > }; > -> + optfclk_pciephy2_div_clk: optfclk_pciephy_div_clk@4a0093b4 { +> + optfclk_pciephy2_div_clk: optfclk_pciephy_div_clk at 4a0093b4 { > + compatible = "ti,gate-clock"; > + clocks = <&optfclk_pciephy_div>; > + #clock-cells = <0>; diff --git a/a/content_digest b/N2/content_digest index 7908ba4..ea0c9f9 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,25 +1,9 @@ "ref\01401345500-20188-1-git-send-email-kishon@ti.com\0" "ref\01401345500-20188-14-git-send-email-kishon@ti.com\0" - "From\0Tero Kristo <t-kristo@ti.com>\0" - "Subject\0Re: [PATCH v2 13/18] ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance\0" + "From\0t-kristo@ti.com (Tero Kristo)\0" + "Subject\0[PATCH v2 13/18] ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance\0" "Date\0Thu, 19 Jun 2014 14:20:39 +0300\0" - "To\0Kishon Vijay Abraham I <kishon@ti.com>" - devicetree@vger.kernel.org - linux-doc@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-omap@vger.kernel.org - linux-pci@vger.kernel.org - " linux-kernel@vger.kernel.org\0" - "Cc\0arnd@arndb.de" - tony@atomide.com - jg1.han@samsung.com - Rajendra Nayak <rnayak@ti.com> - Paul Walmsley <paul@pwsan.com> - Rob Herring <robh+dt@kernel.org> - Pawel Moll <pawel.moll@arm.com> - Mark Rutland <mark.rutland@arm.com> - Kumar Gala <galak@codeaurora.org> - " Keerthy <j-keerthy@ti.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:\n" @@ -55,7 +39,7 @@ "> \t\tti,bit-shift = <8>;\n" "> \t};\n" ">\n" - "> +\toptfclk_pciephy2_32khz: optfclk_pciephy_32khz@4a0093b4 {\n" + "> +\toptfclk_pciephy2_32khz: optfclk_pciephy_32khz at 4a0093b4 {\n" "> +\t\tcompatible = \"ti,gate-clock\";\n" "> +\t\tclocks = <&sys_32k_ck>;\n" "> +\t\t#clock-cells = <0>;\n" @@ -63,14 +47,14 @@ "> +\t\tti,bit-shift = <8>;\n" "> +\t};\n" "> +\n" - "> \toptfclk_pciephy_div: optfclk_pciephy_div@4a00821c {\n" + "> \toptfclk_pciephy_div: optfclk_pciephy_div at 4a00821c {\n" "> \t\tcompatible = \"ti,divider-clock\";\n" "> \t\tclocks = <&apll_pcie_ck>;\n" "> @@ -1191,6 +1199,14 @@\n" "> \t\tti,bit-shift = <9>;\n" "> \t};\n" ">\n" - "> +\toptfclk_pciephy2_clk: optfclk_pciephy_clk@4a0093b4 {\n" + "> +\toptfclk_pciephy2_clk: optfclk_pciephy_clk at 4a0093b4 {\n" "> +\t\tcompatible = \"ti,gate-clock\";\n" "> +\t\tclocks = <&apll_pcie_ck>;\n" "> +\t\t#clock-cells = <0>;\n" @@ -78,14 +62,14 @@ "> +\t\tti,bit-shift = <9>;\n" "> +\t};\n" "> +\n" - "> \toptfclk_pciephy1_div_clk: optfclk_pciephy_div_clk@4a0093b0 {\n" + "> \toptfclk_pciephy1_div_clk: optfclk_pciephy_div_clk at 4a0093b0 {\n" "> \t\tcompatible = \"ti,gate-clock\";\n" "> \t\tclocks = <&optfclk_pciephy_div>;\n" "> @@ -1199,6 +1215,14 @@\n" "> \t\tti,bit-shift = <10>;\n" "> \t};\n" ">\n" - "> +\toptfclk_pciephy2_div_clk: optfclk_pciephy_div_clk@4a0093b4 {\n" + "> +\toptfclk_pciephy2_div_clk: optfclk_pciephy_div_clk at 4a0093b4 {\n" "> +\t\tcompatible = \"ti,gate-clock\";\n" "> +\t\tclocks = <&optfclk_pciephy_div>;\n" "> +\t\t#clock-cells = <0>;\n" @@ -98,4 +82,4 @@ "> \t\tcompatible = \"fixed-factor-clock\";\n" > -d2f25ea9c69898f2b48aefe5e3466191911bf0e07bbf2a06c9e25dbc73484a6b +341a4fefe2981ef7924c3bddd1bb21f1e562cd8e30dccda3908a61402d24e51c
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