diff for duplicates of <53A2E507.7090405@ti.com> diff --git a/a/content_digest b/N1/content_digest index 30c58f8..8506f22 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -6,15 +6,15 @@ "Subject\0Re: [PATCH v2 10/18] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY\0" "Date\0Thu, 19 Jun 2014 16:26:31 +0300\0" "To\0Kishon Vijay Abraham I <kishon@ti.com>" - devicetree@vger.kernel.org - linux-doc@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-omap@vger.kernel.org - linux-pci@vger.kernel.org - " linux-kernel@vger.kernel.org\0" - "Cc\0arnd@arndb.de" - tony@atomide.com - jg1.han@samsung.com + <devicetree@vger.kernel.org> + <linux-doc@vger.kernel.org> + <linux-arm-kernel@lists.infradead.org> + <linux-omap@vger.kernel.org> + <linux-pci@vger.kernel.org> + " <linux-kernel@vger.kernel.org>\0" + "Cc\0<arnd@arndb.de>" + <tony@atomide.com> + <jg1.han@samsung.com> Rajendra Nayak <rnayak@ti.com> Paul Walmsley <paul@pwsan.com> Rob Herring <robh+dt@kernel.org> @@ -90,4 +90,4 @@ ">>>\n" >> -9408685668a98acdac43e2acf1d77f95edfba7c6645f26cb5e1f2ec5d8965d9e +e8a1b0f4b1363b58acd69efa6e80c65164a390de929034500c95622dbc09fc4f
diff --git a/a/1.txt b/N2/1.txt index 8cf40e0..ca860bf 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -51,7 +51,7 @@ be good. >>> reg = <0x021c>, <0x0220>; >>> }; >>> ->>> + optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 { +>>> + optfclk_pciephy_32khz: optfclk_pciephy_32khz at 4a0093b0 { >>> + compatible = "ti,gate-clock"; >>> + clocks = <&sys_32k_ck>; >>> + #clock-cells = <0>; @@ -59,7 +59,7 @@ be good. >>> + ti,bit-shift = <8>; >>> + }; >>> + ->>> optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { +>>> optfclk_pciephy_div: optfclk_pciephy_div at 4a00821c { >>> compatible = "ti,divider-clock"; >>> clocks = <&apll_pcie_ck>; >>> diff --git a/a/content_digest b/N2/content_digest index 30c58f8..38e2ba5 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,25 +2,10 @@ "ref\01401345500-20188-11-git-send-email-kishon@ti.com\0" "ref\053A2C690.1060106@ti.com\0" "ref\053A2E452.5020109@ti.com\0" - "From\0Tero Kristo <t-kristo@ti.com>\0" - "Subject\0Re: [PATCH v2 10/18] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY\0" + "From\0t-kristo@ti.com (Tero Kristo)\0" + "Subject\0[PATCH v2 10/18] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY\0" "Date\0Thu, 19 Jun 2014 16:26:31 +0300\0" - "To\0Kishon Vijay Abraham I <kishon@ti.com>" - devicetree@vger.kernel.org - linux-doc@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-omap@vger.kernel.org - linux-pci@vger.kernel.org - " linux-kernel@vger.kernel.org\0" - "Cc\0arnd@arndb.de" - tony@atomide.com - jg1.han@samsung.com - Rajendra Nayak <rnayak@ti.com> - Paul Walmsley <paul@pwsan.com> - Rob Herring <robh+dt@kernel.org> - Pawel Moll <pawel.moll@arm.com> - Mark Rutland <mark.rutland@arm.com> - " Kumar Gala <galak@codeaurora.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 06/19/2014 04:23 PM, Kishon Vijay Abraham I wrote:\n" @@ -76,7 +61,7 @@ ">>> reg = <0x021c>, <0x0220>;\n" ">>> };\n" ">>>\n" - ">>> + optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 {\n" + ">>> + optfclk_pciephy_32khz: optfclk_pciephy_32khz at 4a0093b0 {\n" ">>> + compatible = \"ti,gate-clock\";\n" ">>> + clocks = <&sys_32k_ck>;\n" ">>> + #clock-cells = <0>;\n" @@ -84,10 +69,10 @@ ">>> + ti,bit-shift = <8>;\n" ">>> + };\n" ">>> +\n" - ">>> optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {\n" + ">>> optfclk_pciephy_div: optfclk_pciephy_div at 4a00821c {\n" ">>> compatible = \"ti,divider-clock\";\n" ">>> clocks = <&apll_pcie_ck>;\n" ">>>\n" >> -9408685668a98acdac43e2acf1d77f95edfba7c6645f26cb5e1f2ec5d8965d9e +9b3b4662a8574a2c6413378d439cb2b1c06bfb461fdebbdfaf178806c0401318
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