From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>,
Leon Alrae <leon.alrae@imgtec.com>
Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com,
QEMU Developers <qemu-devel@nongnu.org>,
Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [Qemu-devel] [PATCH v2 14/22] target-mips: add Addressing and PC-relative instructions
Date: Tue, 24 Jun 2014 07:24:37 -0700 [thread overview]
Message-ID: <53A98A25.1030900@twiddle.net> (raw)
In-Reply-To: <CAFEAcA8hQ412R0wxZWGFYuqgDJLMOrQhBTXeaKxNC3gDoscdXg@mail.gmail.com>
On 06/24/2014 03:00 AM, Peter Maydell wrote:
> On 24 June 2014 10:50, Leon Alrae <leon.alrae@imgtec.com> wrote:
>> On 20/06/2014 21:50, Aurelien Jarno wrote:
>>> I do wonder if we shouldn't use sextract32() instead of open coding that
>>> now that it is available:
>>>
>>> offset = sextract32(ctx->opcode, 0, 19) << 3;
>>
>> This looks better, thanks for the suggestion (but since the offset's
>> size is 18, third argument will be 18, not 19).
>
> This is undefined behaviour in C because of the shift into
> the sign bit. Better to shift first and then signextend:
>
> offset = sextract32(ctx->opcode << 3, 0, 21);
Not true. Because we know from the extract that the value has 13 copies of the
sign bit. Shifting by 3 isn't going to cause problems. It's shifting a
*different* bit into the sign position that's (one's compliment) undefined.
r~
PS: Honestly, all these compilers/sanitizers should grow a "No One's
Compliment" switch to disable all the stupid stuff.
next prev parent reply other threads:[~2014-06-24 14:24 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-11 15:19 [Qemu-devel] [PATCH v2 00/22] target-mips: add MIPS64R6 Instruction Set support Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 01/22] target-mips: define ISA_MIPS64R6 Leon Alrae
2014-06-19 21:06 ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 02/22] target-mips: signal RI Exception on instructions removed in R6 Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 03/22] target-mips: add SELEQZ and SELNEZ instructions Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 04/22] target-mips: move LL and SC instructions Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 05/22] target-mips: extract decode_opc_special* from decode_opc Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 06/22] target-mips: split decode_opc_special* into *_r6 and *_legacy Leon Alrae
2014-06-19 21:06 ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 07/22] target-mips: signal RI Exception on DSP and Loongson instructions Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 08/22] target-mips: move PREF, CACHE, LLD and SCD instructions Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 09/22] target-mips: redefine Integer Multiply and Divide instructions Leon Alrae
2014-06-19 21:06 ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 10/22] target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6 Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 11/22] target-mips: Status.UX/SX/KX enable 32-bit address wrapping Leon Alrae
2014-06-19 21:06 ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 12/22] target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions Leon Alrae
2014-06-11 16:39 ` Richard Henderson
2014-06-12 8:35 ` Leon Alrae
2014-06-12 14:34 ` Richard Henderson
2014-06-19 21:06 ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 13/22] target-mips: add Compact Branches Leon Alrae
2014-06-11 16:52 ` Richard Henderson
2014-06-24 14:03 ` Leon Alrae
2014-06-19 21:06 ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 14/22] target-mips: add Addressing and PC-relative instructions Leon Alrae
2014-06-20 20:50 ` Aurelien Jarno
2014-06-24 9:50 ` Leon Alrae
2014-06-24 10:00 ` Peter Maydell
2014-06-24 14:24 ` Richard Henderson [this message]
2014-06-24 14:54 ` Peter Maydell
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 15/22] softfloat: add functions corresponding to IEEE-2008 min/maxNumMag Leon Alrae
2014-06-19 21:27 ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 16/22] target-mips: add new Floating Point instructions Leon Alrae
2014-06-20 21:14 ` Aurelien Jarno
2014-06-24 12:10 ` Leon Alrae
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 17/22] target-mips: add new Floating Point Comparison instructions Leon Alrae
2014-06-20 21:36 ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 18/22] target-mips: do not allow Status.FR=0 mode in 64-bit FPU Leon Alrae
2014-06-19 21:27 ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 19/22] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions Leon Alrae
2014-06-19 22:22 ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 20/22] mips_malta: update malta's pseudo-bootloader - replace JR with JALR Leon Alrae
2014-06-19 21:27 ` Aurelien Jarno
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 21/22] target-mips: use pointers referring to appropriate decoding function Leon Alrae
2014-06-19 22:18 ` Aurelien Jarno
2014-06-20 4:09 ` Richard Henderson
2014-06-11 15:19 ` [Qemu-devel] [PATCH v2 22/22] target-mips: define a new generic CPU supporting MIPS64R6 Leon Alrae
2014-06-19 22:16 ` Aurelien Jarno
2014-06-24 11:56 ` Leon Alrae
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