From: Stephen Warren <swarren@wwwdotorg.org>
To: Andrew Bresticker <abrestic@chromium.org>
Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
linux-usb@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Randy Dunlap <rdunlap@infradead.org>,
Thierry Reding <thierry.reding@gmail.com>,
Russell King <linux@arm.linux.org.uk>,
Linus Walleij <linus.walleij@linaro.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Mathias Nyman <mathias.nyman@intel.com>,
Grant Likely <grant.likely@linaro.org>,
Alan Stern <stern@rowland.harvard.edu>,
Kishon Vijay Abraham I <kishon@ti.com>,
Arnd Bergmann <arnd@arndb.de>,
bal
Subject: Re: [PATCH v1 4/9] pinctrl: tegra-xusb: Add USB PHY support
Date: Thu, 26 Jun 2014 12:08:57 -0600 [thread overview]
Message-ID: <53AC61B9.5030408@wwwdotorg.org> (raw)
In-Reply-To: <CAL1qeaHhoqEPu-j+drNiRMyeutz=qqZPxSP8H+v-sgjZSfS5tQ@mail.gmail.com>
On 06/25/2014 05:30 PM, Andrew Bresticker wrote:
> On Wed, Jun 25, 2014 at 3:12 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
>>> In addition to the PCIe and SATA PHYs, the XUSB pad controller also
>>> supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
>>> PCIe or SATA lane and is mapped to one of the three UTMI ports.
>>>
>>
>>> diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c
>>
>>> @@ -372,6 +720,193 @@ static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
>>> padctl_writel(padctl, regval, lane->offset);
>>> break;
>>>
>>> + case TEGRA_XUSB_PADCTL_USB3_PORT_NUM:
>>> + if (value >= TEGRA_XUSB_PADCTL_USB3_PORTS) {
>>> + dev_err(padctl->dev, "Invalid USB3 port: %lu\n",
>>> + value);
>>> + return -EINVAL;
>>> + }
>>> + if (!is_pcie_sata_lane(group)) {
>>> + dev_err(padctl->dev,
>>> + "USB3 port not applicable for pin %d\n",
>>> + group);
>>> + return -EINVAL;
>>> + }
>>> + padctl->usb3_ports[value].lane = group;
>>> + break;
>>
>> It feels odd to use pinctrl for a SW-only purpose. In other words, that
>> chunk of code isn't writing the pinconf data to HW, but rather some
>> internal variable.
>
> Well the mapping of lanes to USB3 ports is a hardware property and we
> do use it when programming the hardware later to choose which set of
> lane registers to program given a USB3 port, but it's true that it's
> not some value we program into HW directly.
>
>> Perhaps it would make more sense for the DT binding to represent this
>> data directly in a custom property that's parsed at probe() time. That
>> way, pinctrl only touches "real" HW stuff.
>
> I'm on the fence about this. If you or others feel strongly about
> this then I can make it a separate DT property and move it out of the
> pinctrl properties.
I'd certainly prefer to use pinctrl bindings only for things that get
directly written into HW. Other configuration data should be easy to
retrieve directly from properties.
WARNING: multiple messages have this Message-ID (diff)
From: swarren@wwwdotorg.org (Stephen Warren)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 4/9] pinctrl: tegra-xusb: Add USB PHY support
Date: Thu, 26 Jun 2014 12:08:57 -0600 [thread overview]
Message-ID: <53AC61B9.5030408@wwwdotorg.org> (raw)
In-Reply-To: <CAL1qeaHhoqEPu-j+drNiRMyeutz=qqZPxSP8H+v-sgjZSfS5tQ@mail.gmail.com>
On 06/25/2014 05:30 PM, Andrew Bresticker wrote:
> On Wed, Jun 25, 2014 at 3:12 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
>>> In addition to the PCIe and SATA PHYs, the XUSB pad controller also
>>> supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
>>> PCIe or SATA lane and is mapped to one of the three UTMI ports.
>>>
>>
>>> diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c
>>
>>> @@ -372,6 +720,193 @@ static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
>>> padctl_writel(padctl, regval, lane->offset);
>>> break;
>>>
>>> + case TEGRA_XUSB_PADCTL_USB3_PORT_NUM:
>>> + if (value >= TEGRA_XUSB_PADCTL_USB3_PORTS) {
>>> + dev_err(padctl->dev, "Invalid USB3 port: %lu\n",
>>> + value);
>>> + return -EINVAL;
>>> + }
>>> + if (!is_pcie_sata_lane(group)) {
>>> + dev_err(padctl->dev,
>>> + "USB3 port not applicable for pin %d\n",
>>> + group);
>>> + return -EINVAL;
>>> + }
>>> + padctl->usb3_ports[value].lane = group;
>>> + break;
>>
>> It feels odd to use pinctrl for a SW-only purpose. In other words, that
>> chunk of code isn't writing the pinconf data to HW, but rather some
>> internal variable.
>
> Well the mapping of lanes to USB3 ports is a hardware property and we
> do use it when programming the hardware later to choose which set of
> lane registers to program given a USB3 port, but it's true that it's
> not some value we program into HW directly.
>
>> Perhaps it would make more sense for the DT binding to represent this
>> data directly in a custom property that's parsed at probe() time. That
>> way, pinctrl only touches "real" HW stuff.
>
> I'm on the fence about this. If you or others feel strongly about
> this then I can make it a separate DT property and move it out of the
> pinctrl properties.
I'd certainly prefer to use pinctrl bindings only for things that get
directly written into HW. Other configuration data should be easy to
retrieve directly from properties.
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Warren <swarren@wwwdotorg.org>
To: Andrew Bresticker <abrestic@chromium.org>
Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
linux-usb@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Randy Dunlap <rdunlap@infradead.org>,
Thierry Reding <thierry.reding@gmail.com>,
Russell King <linux@arm.linux.org.uk>,
Linus Walleij <linus.walleij@linaro.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Mathias Nyman <mathias.nyman@intel.com>,
Grant Likely <grant.likely@linaro.org>,
Alan Stern <stern@rowland.harvard.edu>,
Kishon Vijay Abraham I <kishon@ti.com>,
Arnd Bergmann <arnd@arndb.de>,
balbi@ti.com
Subject: Re: [PATCH v1 4/9] pinctrl: tegra-xusb: Add USB PHY support
Date: Thu, 26 Jun 2014 12:08:57 -0600 [thread overview]
Message-ID: <53AC61B9.5030408@wwwdotorg.org> (raw)
In-Reply-To: <CAL1qeaHhoqEPu-j+drNiRMyeutz=qqZPxSP8H+v-sgjZSfS5tQ@mail.gmail.com>
On 06/25/2014 05:30 PM, Andrew Bresticker wrote:
> On Wed, Jun 25, 2014 at 3:12 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
>>> In addition to the PCIe and SATA PHYs, the XUSB pad controller also
>>> supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
>>> PCIe or SATA lane and is mapped to one of the three UTMI ports.
>>>
>>
>>> diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c
>>
>>> @@ -372,6 +720,193 @@ static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
>>> padctl_writel(padctl, regval, lane->offset);
>>> break;
>>>
>>> + case TEGRA_XUSB_PADCTL_USB3_PORT_NUM:
>>> + if (value >= TEGRA_XUSB_PADCTL_USB3_PORTS) {
>>> + dev_err(padctl->dev, "Invalid USB3 port: %lu\n",
>>> + value);
>>> + return -EINVAL;
>>> + }
>>> + if (!is_pcie_sata_lane(group)) {
>>> + dev_err(padctl->dev,
>>> + "USB3 port not applicable for pin %d\n",
>>> + group);
>>> + return -EINVAL;
>>> + }
>>> + padctl->usb3_ports[value].lane = group;
>>> + break;
>>
>> It feels odd to use pinctrl for a SW-only purpose. In other words, that
>> chunk of code isn't writing the pinconf data to HW, but rather some
>> internal variable.
>
> Well the mapping of lanes to USB3 ports is a hardware property and we
> do use it when programming the hardware later to choose which set of
> lane registers to program given a USB3 port, but it's true that it's
> not some value we program into HW directly.
>
>> Perhaps it would make more sense for the DT binding to represent this
>> data directly in a custom property that's parsed at probe() time. That
>> way, pinctrl only touches "real" HW stuff.
>
> I'm on the fence about this. If you or others feel strongly about
> this then I can make it a separate DT property and move it out of the
> pinctrl properties.
I'd certainly prefer to use pinctrl bindings only for things that get
directly written into HW. Other configuration data should be easy to
retrieve directly from properties.
next prev parent reply other threads:[~2014-06-26 18:08 UTC|newest]
Thread overview: 103+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-18 6:16 [PATCH v1 0/9] Tegra XHCI support Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
2014-06-18 6:16 ` [PATCH v1 2/9] mailbox: Add NVIDIA Tegra XUSB mailbox driver Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
[not found] ` <1403072180-4944-3-git-send-email-abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-06-25 22:02 ` Stephen Warren
2014-06-25 22:02 ` Stephen Warren
2014-06-25 22:02 ` Stephen Warren
2014-06-25 23:07 ` Andrew Bresticker
2014-06-25 23:07 ` Andrew Bresticker
2014-06-18 6:16 ` [PATCH v1 3/9] of: Update Tegra XUSB pad controller binding for USB Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
[not found] ` <1403072180-4944-4-git-send-email-abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-06-25 21:46 ` Stephen Warren
2014-06-25 21:46 ` Stephen Warren
2014-06-25 21:46 ` Stephen Warren
2014-06-25 22:25 ` Andrew Bresticker
2014-06-25 22:25 ` Andrew Bresticker
2014-06-26 20:00 ` Stephen Warren
2014-06-26 20:00 ` Stephen Warren
2014-06-18 6:16 ` [PATCH v1 5/9] of: Add NVIDIA Tegra XHCI controller binding Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
[not found] ` <1403072180-4944-6-git-send-email-abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-06-25 21:52 ` Stephen Warren
2014-06-25 21:52 ` Stephen Warren
2014-06-25 21:52 ` Stephen Warren
2014-06-25 23:01 ` Andrew Bresticker
2014-06-25 23:01 ` Andrew Bresticker
[not found] ` <CAL1qeaG=nLxDHrsVuuL9c-JdKB+TrNN785+8v=hb0MAFJ=5juw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-06-25 23:13 ` Stephen Warren
2014-06-25 23:13 ` Stephen Warren
2014-06-25 23:13 ` Stephen Warren
2014-06-25 21:54 ` Stephen Warren
2014-06-25 21:54 ` Stephen Warren
2014-06-25 21:54 ` Stephen Warren
[not found] ` <53AB4530.2050106-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-06-25 23:02 ` Andrew Bresticker
2014-06-25 23:02 ` Andrew Bresticker
2014-06-25 23:02 ` Andrew Bresticker
[not found] ` <CAL1qeaHThKVBoY0fikFCh9X00BFNJ=XKfovOBwztEyOVjHBLjg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-06-25 23:14 ` Stephen Warren
2014-06-25 23:14 ` Stephen Warren
2014-06-25 23:14 ` Stephen Warren
[not found] ` <1403072180-4944-1-git-send-email-abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-06-18 6:16 ` [PATCH v1 1/9] of: Add NVIDIA Tegra XUSB mailbox binding Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
[not found] ` <1403072180-4944-2-git-send-email-abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-06-25 21:42 ` Stephen Warren
2014-06-25 21:42 ` Stephen Warren
2014-06-25 21:42 ` Stephen Warren
[not found] ` <53AB422E.4040707-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-06-25 22:37 ` Andrew Bresticker
2014-06-25 22:37 ` Andrew Bresticker
2014-06-25 22:37 ` Andrew Bresticker
[not found] ` <CAL1qeaFPjq9nqA2GDZZW+=DZsddWCkUjJcnRsfPkBWj8gmFsiw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-06-25 23:00 ` Stephen Warren
2014-06-25 23:00 ` Stephen Warren
2014-06-25 23:00 ` Stephen Warren
2014-06-18 6:16 ` [PATCH v1 4/9] pinctrl: tegra-xusb: Add USB PHY support Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
2014-06-25 22:12 ` Stephen Warren
2014-06-25 22:12 ` Stephen Warren
2014-06-25 23:30 ` Andrew Bresticker
2014-06-25 23:30 ` Andrew Bresticker
2014-06-25 23:30 ` Andrew Bresticker
2014-06-26 18:08 ` Stephen Warren [this message]
2014-06-26 18:08 ` Stephen Warren
2014-06-26 18:08 ` Stephen Warren
2014-06-27 21:22 ` Andrew Bresticker
2014-06-27 21:22 ` Andrew Bresticker
2014-06-27 21:22 ` Andrew Bresticker
2014-06-27 15:00 ` Felipe Balbi
2014-06-27 15:00 ` Felipe Balbi
2014-06-27 15:00 ` Felipe Balbi
2014-06-27 16:05 ` Stephen Warren
2014-06-27 16:05 ` Stephen Warren
2014-06-18 6:16 ` [PATCH v1 6/9] usb: xhci: Add NVIDIA Tegra XHCI host-controller driver Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
[not found] ` <1403072180-4944-7-git-send-email-abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2014-06-20 16:58 ` Julius Werner
2014-06-20 16:58 ` Julius Werner
2014-06-20 16:58 ` Julius Werner
[not found] ` <CAODwPW-HSY3RoBi9VEhHSJ98drTsdche-2=mKfAViXWaUa3X1g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-07-08 21:52 ` Andrew Bresticker
2014-07-08 21:52 ` Andrew Bresticker
2014-07-08 21:52 ` Andrew Bresticker
[not found] ` <CAL1qeaHT8Yz7kRY3Qm5i+bYCF4D5BT=BVZ6BMfQufyaQFkt0mw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-07-09 14:08 ` Alan Stern
2014-07-09 14:08 ` Alan Stern
2014-07-09 14:08 ` Alan Stern
[not found] ` <Pine.LNX.4.44L0.1407091001150.873-100000-IYeN2dnnYyZXsRXLowluHWD2FQJk+8+b@public.gmane.org>
2014-07-10 10:40 ` Arnd Bergmann
2014-07-10 10:40 ` Arnd Bergmann
2014-07-10 10:40 ` Arnd Bergmann
2014-06-25 22:37 ` Stephen Warren
2014-06-25 22:37 ` Stephen Warren
2014-06-26 0:06 ` Andrew Bresticker
2014-06-26 0:06 ` Andrew Bresticker
[not found] ` <CAL1qeaFhfYdW06Md10eGVYWBrRR+f1yykVYHNp5+9-t1C9joPQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-06-26 18:07 ` Stephen Warren
2014-06-26 18:07 ` Stephen Warren
2014-06-26 18:07 ` Stephen Warren
2014-06-27 21:19 ` Andrew Bresticker
2014-06-27 21:19 ` Andrew Bresticker
2014-06-27 22:01 ` Stephen Warren
2014-06-27 22:01 ` Stephen Warren
2014-06-18 6:16 ` [PATCH v1 7/9] ARM: tegra: Add Tegra124 XUSB mailbox and XHCI controller Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
2014-06-18 6:16 ` [PATCH v1 8/9] ARM: tegra: jetson-tk1: Add XHCI support Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
2014-06-18 6:16 ` [PATCH v1 9/9] ARM: tegra: venice2: " Andrew Bresticker
2014-06-18 6:16 ` Andrew Bresticker
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