diff for duplicates of <53ADDAEF.2070805@wwwdotorg.org> diff --git a/a/1.txt b/N1/1.txt index 602b3e4..0edbbdc 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,5 +1,5 @@ On 06/27/2014 10:58 AM, Thierry Reding wrote: -> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> From: Thierry Reding <treding@nvidia.com> > > Add device tree nodes for the legacy interrupt controller so that the > driver can get the register ranges from device tree rather than hard- @@ -7,7 +7,7 @@ On 06/27/2014 10:58 AM, Thierry Reding wrote: > diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi -> + interrupt-controller@60004000 { +> + interrupt-controller at 60004000 { > + compatible = "nvidia,tegra20-ictlr"; > + reg = <0x60004000 0x40 /* primary controller */ > + 0x60004100 0x40 /* secondary controller */ @@ -20,7 +20,7 @@ The quinary controller doesn't exist on Tegra20. > diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi -> + interrupt-controller@60004000 { +> + interrupt-controller at 60004000 { > + compatible = "nvidia,tegra20-ictlr"; At the least, each SoC should have an SoC-specific compatible value in diff --git a/a/content_digest b/N1/content_digest index f047c47..1b670a3 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,16 +1,13 @@ "ref\01403888329-24755-1-git-send-email-thierry.reding@gmail.com\0" "ref\01403888329-24755-2-git-send-email-thierry.reding@gmail.com\0" - "ref\01403888329-24755-2-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" - "From\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>\0" - "Subject\0Re: [RFC 2/4] ARM: tegra: Add legacy interrupt controller nodes\0" + "From\0swarren@wwwdotorg.org (Stephen Warren)\0" + "Subject\0[RFC 2/4] ARM: tegra: Add legacy interrupt controller nodes\0" "Date\0Fri, 27 Jun 2014 14:58:23 -0600\0" - "To\0Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" - "Cc\0linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 06/27/2014 10:58 AM, Thierry Reding wrote:\n" - "> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> From: Thierry Reding <treding@nvidia.com>\n" "> \n" "> Add device tree nodes for the legacy interrupt controller so that the\n" "> driver can get the register ranges from device tree rather than hard-\n" @@ -18,7 +15,7 @@ "\n" "> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi\n" "\n" - "> +\tinterrupt-controller@60004000 {\n" + "> +\tinterrupt-controller at 60004000 {\n" "> +\t\tcompatible = \"nvidia,tegra20-ictlr\";\n" "> +\t\treg = <0x60004000 0x40 /* primary controller */\n" "> +\t\t 0x60004100 0x40 /* secondary controller */\n" @@ -31,7 +28,7 @@ "\n" "> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi\n" "\n" - "> +\tinterrupt-controller@60004000 {\n" + "> +\tinterrupt-controller at 60004000 {\n" "> +\t\tcompatible = \"nvidia,tegra20-ictlr\";\n" "\n" "At the least, each SoC should have an SoC-specific compatible value in\n" @@ -44,4 +41,4 @@ "Tegra20 compatible (or all Tegra30 compatible given the 4-vs-5\n" controllers difference). -77e412362da9d3711c2b52a2a7ac0cd7939bef735653e89d373d8a659849c596 +e7b2e912348e5aae152d9711b1058cb997720680fac43342d4d2666a0752a7e2
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