From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tomasz Figa Subject: Re: [PATCH v2] clk: exynos4: Add PPMU IP block source clocks. Date: Mon, 30 Jun 2014 15:47:42 +0200 Message-ID: <53B16A7E.7020208@samsung.com> References: <1401190028-21020-1-git-send-email-jonghwa3.lee@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: Received: from mailout3.w1.samsung.com ([210.118.77.13]:14976 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752104AbaF3NsS (ORCPT ); Mon, 30 Jun 2014 09:48:18 -0400 In-reply-to: <1401190028-21020-1-git-send-email-jonghwa3.lee@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org List-Id: linux-samsung-soc@vger.kernel.org To: Jonghwa Lee , linux-kernel@vger.kernel.org Cc: linux-samsung-soc@vger.kernel.org, mturquette@linaro.org, Chanwoo Choi , Myungjoo Ham On 27.05.2014 13:27, Jonghwa Lee wrote: > Exynos4 has saveral PPMUs and each of them has operation clock which > can be gated through CMU's SFR control. > > New clocks are listed below. All clocks are added as a gate-typed clock. > > CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L, > CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1, > CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU, > CLK_PPMUACP, > > Signed-off-by: Jonghwa Lee > Signed-off-by: Chanwoo Choi > Signed-off-by: Myungjoo Ham > --- > V2 : > - Change clock definition order. > > drivers/clk/samsung/clk-exynos4.c | 19 +++++++++++++++++++ > include/dt-bindings/clock/exynos4.h | 18 ++++++++++++++++++ > 2 files changed, 37 insertions(+) Applied for v3.17. Best regards, Tomasz