From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: [PATCH RFC 3/9] xen: Force-enable relevant MSR
 events; optimize the number of sent MSR events
Date: Wed, 2 Jul 2014 16:35:42 +0100
Message-ID: <53B426CE.6070400@citrix.com>
References: <1404308041-15461-1-git-send-email-rcojocaru@bitdefender.com>
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To: Razvan Cojocaru <rcojocaru@bitdefender.com>, xen-devel@lists.xen.org
Cc: tim@xen.org
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On 02/07/14 14:33, Razvan Cojocaru wrote:
> Vmx_disable_intercept_for_msr() will now refuse to disable interception of
> MSRs needed by the memory introspection library.
>
> Signed-off-by: Razvan Cojocaru <rcojocaru@bitdefender.com>
> ---
>  xen/arch/x86/hvm/vmx/vmcs.c |   19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
> index 8ffc562..eb3f030 100644
> --- a/xen/arch/x86/hvm/vmx/vmcs.c
> +++ b/xen/arch/x86/hvm/vmx/vmcs.c
> @@ -700,6 +700,25 @@ void vmx_disable_intercept_for_msr(struct vcpu *v, u32 msr, int type)
>      if ( msr_bitmap == NULL )
>          return;
>  
> +    /* Filter out MSR-s needed by the memory introspection engine */
> +    switch ( msr )
> +    {
> +    case MSR_IA32_SYSENTER_EIP:
> +    case MSR_IA32_SYSENTER_ESP:
> +    case MSR_IA32_SYSENTER_CS:
> +    case MSR_IA32_MC0_CTL:
> +    case MSR_STAR:
> +    case MSR_LSTAR:
> +

Given the performance implications of forcing interception of these
MSRs, it would be gated on mem_access being active for the domain.

> +        printk("Warning: cannot disable the interception of MSR "
> +            "0x%08x because it is needed by the memory introspection "
> +            "engine\n", msr);
> +        return;

gdprintk() please, and a rather shorter message.

~Andrew

> +
> +    default:
> +        break;
> +    }
> +
>      /*
>       * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
>       * have the write-low and read-high bitmap offsets the wrong way round.