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From: Julien Grall <julien.grall@linaro.org>
To: Stefano Stabellini <stefano.stabellini@eu.citrix.com>,
	xen-devel@lists.xensource.com
Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com
Subject: Re: [PATCH v7 3/6] xen/arm: inflight irqs during migration
Date: Fri, 04 Jul 2014 11:26:54 +0100	[thread overview]
Message-ID: <53B6816E.6080600@linaro.org> (raw)
In-Reply-To: <1404406394-18231-3-git-send-email-stefano.stabellini@eu.citrix.com>

On 07/03/2014 05:53 PM, Stefano Stabellini wrote:
>  static void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n)
>  {
>      const unsigned long mask = r;
> @@ -598,35 +638,60 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
>          goto write_ignore;
>  
>      case GICD_ITARGETSR + 8 ... GICD_ITARGETSRN:
> +    {
> +        /* unsigned long needed for find_next_bit */
> +        unsigned long target;
> +        int i;
>          if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
>          rank = vgic_rank_offset(v, 8, gicd_reg - GICD_ITARGETSR);
>          if ( rank == NULL) goto write_ignore;
>          /* 8-bit vcpu mask for this domain */
>          BUG_ON(v->domain->max_vcpus > 8);
> -        tr = (1 << v->domain->max_vcpus) - 1;
> +        target = (1 << v->domain->max_vcpus) - 1;
>          if ( dabt.size == 2 )
> -            tr = tr | (tr << 8) | (tr << 16) | (tr << 24);
> +            target = target | (target << 8) | (target << 16) | (target << 24);
>          else
> -            tr = (tr << (8 * (offset & 0x3)));
> -        tr &= *r;
> +            target = (target << (8 * (offset & 0x3)));
> +        target &= *r;
>          /* ignore zero writes */
> -        if ( !tr )
> +        if ( !target )
>              goto write_ignore;
>          /* For word reads ignore writes where any single byte is zero */
>          if ( dabt.size == 2 &&
> -            !((tr & 0xff) && (tr & (0xff << 8)) &&
> -             (tr & (0xff << 16)) && (tr & (0xff << 24))))
> +            !((target & 0xff) && (target & (0xff << 8)) &&
> +             (target & (0xff << 16)) && (target & (0xff << 24))))
>              goto write_ignore;
>          vgic_lock_rank(v, rank);
> +        i = 0;
> +        while ( (i = find_next_bit(&target, 32, i)) < 32 )
> +        {
> +            unsigned int irq, target, old_target;

target is already defined above, and this will shadow this previous
definition. I would rename one of them to avoid coding error later.

-- 
Julien Grall

  reply	other threads:[~2014-07-04 10:26 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-07-03 16:52 [PATCH v7 0/6] vgic emulation and GICD_ITARGETSR Stefano Stabellini
2014-07-03 16:53 ` [PATCH v7 1/6] xen/arm: observe itargets setting in vgic_enable_irqs and vgic_disable_irqs Stefano Stabellini
2014-07-03 16:53 ` [PATCH v7 2/6] xen/arm: move setting GIC_IRQ_GUEST_QUEUED earlier Stefano Stabellini
2014-07-04 10:23   ` Julien Grall
2014-07-09 15:38   ` Ian Campbell
2014-07-03 16:53 ` [PATCH v7 3/6] xen/arm: inflight irqs during migration Stefano Stabellini
2014-07-04 10:26   ` Julien Grall [this message]
2014-07-03 16:53 ` [PATCH v7 4/6] xen/arm: support irq delivery to vcpu > 0 Stefano Stabellini
2014-07-04 10:28   ` Julien Grall
2014-07-09 15:41   ` Ian Campbell
2014-07-03 16:53 ` [PATCH v7 5/6] xen/arm: physical irq follow virtual irq Stefano Stabellini
2014-07-04 10:51   ` Julien Grall
2014-07-10 15:59     ` Ian Campbell
2014-07-10 17:47     ` Stefano Stabellini
2014-07-03 16:53 ` [PATCH v7 6/6] xen: introduce sched_move_irqs Stefano Stabellini

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