From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59599) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X4QRX-0001sT-4j for qemu-devel@nongnu.org; Tue, 08 Jul 2014 04:08:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X4QRQ-000630-WE for qemu-devel@nongnu.org; Tue, 08 Jul 2014 04:08:03 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:50603) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X4QRQ-00062w-Q9 for qemu-devel@nongnu.org; Tue, 08 Jul 2014 04:07:56 -0400 Message-ID: <53BBA6D6.8080507@imgtec.com> Date: Tue, 8 Jul 2014 09:07:50 +0100 From: Leon Alrae MIME-Version: 1.0 References: <1403189143-54609-1-git-send-email-leon.alrae@imgtec.com> <1403189143-54609-9-git-send-email-leon.alrae@imgtec.com> <20140619221347.GA22451@ohm.rr44.fr> In-Reply-To: <20140619221347.GA22451@ohm.rr44.fr> Content-Type: text/plain; charset="ISO-8859-15" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 08/12] target-mips: add BadInstr and BadInstrP support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, qemu-devel@nongnu.org On 19/06/2014 23:13, Aurelien Jarno wrote: > I don't think this should implemented that way, as it would have a > significant impact on the performances. Given we have the fault address > (we fill EPC), we can fetch the corresponding opcode. There might be > some code change to do for the branches, so that we can get the > informations we need from re-translation (this might also simplify the > current branches code). I changed the BadInstr implementation in v2. Now the instruction word is fetched when we have the exception (and the valid instruction word is available), so we don't have to generate code to save the last instruction. The same has been done for BadInstrP and the branch prior to the delay slot. Thanks, Leon