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Date: Tue, 8 Jul 2014 09:18:22 +0100
From: Leon Alrae <leon.alrae@imgtec.com>
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Subject: Re: [Qemu-devel] [PATCH 01/12] target-mips: add KScratch registers
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To: Aurelien Jarno <aurelien@aurel32.net>
Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, qemu-devel@nongnu.org

On 20/06/2014 23:02, Aurelien Jarno wrote:
>> @@ -5198,6 +5199,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
>>              gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
>>              rn = "DESAVE";
>>              break;
>> +        case 2 ... 7:
>> +            tcg_gen_ld_tl(arg, cpu_env,
>> +                          offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
>> +            tcg_gen_ext32s_tl(arg, arg);
>> +            rn = "KScratch";
>> +            break;
> 
> This change the behaviour of existing CPU which don't implement scratch
> registers. Before it would generate an RI exception, and after the
> patch, it would simply leave the register unchanged.
> 
> The architecture manuals says in that case the result is UNDEFINED, so
> that might be fine, that said it also says this instruction could
> generate an RI exception, and I wouldn't be surprised real silicon
> actually generate such an exception.

On the real HW - reads from an unimplemented cp0 register return
0xffffffff (in R6 it will be 0) and writes are just ignored, there is no
RI exception. In v2 I updated the behaviour for the new registers only.
I think the same changes will be needed for the existing registers, but
this is out of the current patch series scope - I plan to do this later.

Thanks,
Leon