From: Leon Alrae <leon.alrae@imgtec.com>
To: Richard Henderson <rth@twiddle.net>, qemu-devel@nongnu.org
Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH 02/12] target-mips: update cpu_save/cpu_load to support KScratch registers
Date: Tue, 8 Jul 2014 09:31:18 +0100 [thread overview]
Message-ID: <53BBAC56.8060509@imgtec.com> (raw)
In-Reply-To: <53A32158.4060805@twiddle.net>
On 19/06/2014 18:43, Richard Henderson wrote:
> You must update CPU_SAVE_VERSION when you change the contents of the save data.
>
> For extra credit, consider updating target-mips to VMStateDescription structure(s).
>
>
> r~
>
v2 contains updated CPU_SAVE_VERSION.
VMStateDescription structures sound like nice to have in target-mips -
at the moment I'm not able to look at this, but I'll keep that in mind.
Thanks,
Leon
next prev parent reply other threads:[~2014-07-08 8:31 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-19 14:45 [Qemu-devel] [PATCH 00/12] implement features required in MIPS64 Release 6 Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 01/12] target-mips: add KScratch registers Leon Alrae
2014-06-20 22:02 ` Aurelien Jarno
2014-07-08 8:18 ` Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 02/12] target-mips: update cpu_save/cpu_load to support " Leon Alrae
2014-06-19 17:43 ` Richard Henderson
2014-07-08 8:31 ` Leon Alrae [this message]
2014-06-19 14:45 ` [Qemu-devel] [PATCH 03/12] target-mips: distinguish between data load and instruction fetch Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 04/12] target-mips: add RI and XI fields to TLB entry Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 05/12] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1} Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 06/12] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 07/12] target-mips: add TLBINV support Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 08/12] target-mips: add BadInstr and BadInstrP support Leon Alrae
2014-06-19 22:13 ` Aurelien Jarno
2014-07-08 8:07 ` Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 09/12] target-mips: save cpu state if instruction can cause an exception Leon Alrae
2014-06-19 22:13 ` Aurelien Jarno
2014-06-19 14:45 ` [Qemu-devel] [PATCH 10/12] target-mips: update cpu_save/cpu_load to support BadInstr registers Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 11/12] target-mips: enable features in MIPS32R5-generic core Leon Alrae
2014-06-19 14:45 ` [Qemu-devel] [PATCH 12/12] target-mips: enable features in MIPS64R6-generic core Leon Alrae
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