From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47680) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X4XlX-00029p-Pu for qemu-devel@nongnu.org; Tue, 08 Jul 2014 11:57:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X4XlS-00070D-NI for qemu-devel@nongnu.org; Tue, 08 Jul 2014 11:57:11 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:3245) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X4XlS-0006zy-GZ for qemu-devel@nongnu.org; Tue, 08 Jul 2014 11:57:06 -0400 Message-ID: <53BC14C7.5030809@imgtec.com> Date: Tue, 8 Jul 2014 16:56:55 +0100 From: Leon Alrae MIME-Version: 1.0 References: <1404806257-28048-1-git-send-email-leon.alrae@imgtec.com> <1404806257-28048-9-git-send-email-leon.alrae@imgtec.com> <53BBE797.4030008@imgtec.com> In-Reply-To: <53BBE797.4030008@imgtec.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 8/9] target-mips: add BadInstr and BadInstrP support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: James Hogan , qemu-devel@nongnu.org Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, aurelien@aurel32.net Hi James, On 08/07/2014 13:44, James Hogan wrote: > Hi Leon, > > On 08/07/14 08:57, Leon Alrae wrote: >> BadInstr Register (CP0 Register 8, Select 1) >> The BadInstr register is a read-only register that capture the most recent >> instruction which caused an exception. >> >> BadInstrP Register (CP0 Register 8, Select 2) >> The BadInstrP register contains the prior branch instruction, when the >> faulting instruction is in a branch delay slot. >> >> Using error_code to indicate whether AdEL or TLBL was triggered during >> instruction fetch, in this case BadInstr is not updated as valid instruction >> word is not available. >> >> Signed-off-by: Leon Alrae >> --- >> target-mips/cpu.h | 6 +++ >> target-mips/helper.c | 44 ++++++++++++++++++++++++-- >> target-mips/op_helper.c | 17 +++++++++- >> target-mips/translate.c | 80 +++++++++++++++++++++++++++++++++++++++++++--- >> 4 files changed, 136 insertions(+), 11 deletions(-) >> >> diff --git a/target-mips/cpu.h b/target-mips/cpu.h >> index bc52222..656f5ca 100644 >> --- a/target-mips/cpu.h >> +++ b/target-mips/cpu.h >> @@ -177,6 +177,8 @@ struct TCState { >> target_ulong CP0_TCScheFBack; >> int32_t CP0_Debug_tcstatus; >> target_ulong CP0_UserLocal; >> + uint32_t CP0_BadInstr; >> + uint32_t CP0_BadInstrP; > > According to the PRA, BadInstr/BadInstrP are instantiated per VPE, so > shouldn't these be in struct CPUMIPSState? > > Cheers > James > Thanks for pointing this out - I'll correct it in the next version. Regards, Leon