From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Message-ID: <53C05DD8.9050500@gmx.de> Date: Fri, 11 Jul 2014 23:57:44 +0200 From: Hartmut Knaack MIME-Version: 1.0 To: =?UTF-8?B?SGVpa28gU3TDvGJuZXI=?= , Jonathan Cameron CC: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , =?UTF-8?B?ImVkZGllKOiUoeaeqyki?= , huangtao@rock-chips.com Subject: Re: [PATCH 2/2] dt-bindings: document Rockchip saradc References: <2959154.xc8BQActsn@diego> <3591595.sBj6Zqo42A@diego> In-Reply-To: <3591595.sBj6Zqo42A@diego> Content-Type: text/plain; charset=UTF-8 List-ID: Heiko Stübner schrieb: > This add the necessary binding documentation for the saradc found in all recent > processors from Rockchip. > > Signed-off-by: Heiko Stuebner > --- Spotted some typos, see inline. > .../bindings/iio/adc/rockchip-saradc.txt | 28 ++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt > > diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt > new file mode 100644 > index 0000000..603ac9c > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt > @@ -0,0 +1,28 @@ > +Rockhip Successive Approximation Register (SAR) A/D Converter bindings Should be "Rockchip". > + > +Required properties: > +- compatible: Should be "rockchip,saradc" > +- reg: physical base address of the controller and length of memory mapped > + region. > +- interrupts: The interrupt number to the cpu. The interrupt specifier format > + depends on the interrupt controller. > +- clocks: Must contain an entry for each entry in clock-names. > +- clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk" for > + the peripheral clock. > +- vref-supply: The regulator supply ADC refrence voltage. ... reference voltage. > +- #io-channel-cells: Should be 1, see ../iio-bindings.txt > + > +Optional properties : > +- clock-frequency : converter frequency in Hz. If omitted, 1MHz is used. > + > +Example: > + saradc: saradc@2006c000 { > + compatible = "rockchip,saradc"; > + reg = <0x2006c000 0x100>; > + interrupts = ; > + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; > + clock-names = "saradc", "apb_pclk"; > + #io-channel-cells = <1>; > + vref-supply = <&vcc18>; > + clock-frequency = <1000000>; > + }; From mboxrd@z Thu Jan 1 00:00:00 1970 From: knaack.h@gmx.de (Hartmut Knaack) Date: Fri, 11 Jul 2014 23:57:44 +0200 Subject: [PATCH 2/2] dt-bindings: document Rockchip saradc In-Reply-To: <3591595.sBj6Zqo42A@diego> References: <2959154.xc8BQActsn@diego> <3591595.sBj6Zqo42A@diego> Message-ID: <53C05DD8.9050500@gmx.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Heiko St?bner schrieb: > This add the necessary binding documentation for the saradc found in all recent > processors from Rockchip. > > Signed-off-by: Heiko Stuebner > --- Spotted some typos, see inline. > .../bindings/iio/adc/rockchip-saradc.txt | 28 ++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt > > diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt > new file mode 100644 > index 0000000..603ac9c > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt > @@ -0,0 +1,28 @@ > +Rockhip Successive Approximation Register (SAR) A/D Converter bindings Should be "Rockchip". > + > +Required properties: > +- compatible: Should be "rockchip,saradc" > +- reg: physical base address of the controller and length of memory mapped > + region. > +- interrupts: The interrupt number to the cpu. The interrupt specifier format > + depends on the interrupt controller. > +- clocks: Must contain an entry for each entry in clock-names. > +- clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk" for > + the peripheral clock. > +- vref-supply: The regulator supply ADC refrence voltage. ... reference voltage. > +- #io-channel-cells: Should be 1, see ../iio-bindings.txt > + > +Optional properties : > +- clock-frequency : converter frequency in Hz. If omitted, 1MHz is used. > + > +Example: > + saradc: saradc at 2006c000 { > + compatible = "rockchip,saradc"; > + reg = <0x2006c000 0x100>; > + interrupts = ; > + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; > + clock-names = "saradc", "apb_pclk"; > + #io-channel-cells = <1>; > + vref-supply = <&vcc18>; > + clock-frequency = <1000000>; > + }; From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hartmut Knaack Subject: Re: [PATCH 2/2] dt-bindings: document Rockchip saradc Date: Fri, 11 Jul 2014 23:57:44 +0200 Message-ID: <53C05DD8.9050500@gmx.de> References: <2959154.xc8BQActsn@diego> <3591595.sBj6Zqo42A@diego> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <3591595.sBj6Zqo42A@diego> Sender: linux-iio-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: =?UTF-8?B?SGVpa28gU3TDvGJuZXI=?= , Jonathan Cameron Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , =?UTF-8?B?ImVkZGllKOiUoeaeqyki?= , huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org List-Id: devicetree@vger.kernel.org Heiko St=C3=BCbner schrieb: > This add the necessary binding documentation for the saradc found in = all recent > processors from Rockchip. > > Signed-off-by: Heiko Stuebner > --- Spotted some typos, see inline. > .../bindings/iio/adc/rockchip-saradc.txt | 28 ++++++++++++= ++++++++++ > 1 file changed, 28 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iio/adc/rockchi= p-saradc.txt > > diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-sarad= c.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt > new file mode 100644 > index 0000000..603ac9c > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt > @@ -0,0 +1,28 @@ > +Rockhip Successive Approximation Register (SAR) A/D Converter bindin= gs Should be "Rockchip". > + > +Required properties: > +- compatible: Should be "rockchip,saradc" > +- reg: physical base address of the controller and length of memory = mapped > + region. > +- interrupts: The interrupt number to the cpu. The interrupt specifi= er format > + depends on the interrupt controller. > +- clocks: Must contain an entry for each entry in clock-names. > +- clock-names: Shall be "saradc" for the converter-clock, and "apb_p= clk" for > + the peripheral clock. > +- vref-supply: The regulator supply ADC refrence voltage. =2E.. reference voltage. > +- #io-channel-cells: Should be 1, see ../iio-bindings.txt > + > +Optional properties : > +- clock-frequency : converter frequency in Hz. If omitted, 1MHz is u= sed. > + > +Example: > + saradc: saradc@2006c000 { > + compatible =3D "rockchip,saradc"; > + reg =3D <0x2006c000 0x100>; > + interrupts =3D ; > + clocks =3D <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; > + clock-names =3D "saradc", "apb_pclk"; > + #io-channel-cells =3D <1>; > + vref-supply =3D <&vcc18>; > + clock-frequency =3D <1000000>; > + };