Re: [Qemu-devel] [PATCH v2 15/15] target-tricore: Add instructions of SR opcode format

[Richard Henderson <rth@twiddle.net>]

On 07/14/2014 10:41 AM, Bastian Koppelmann wrote:
> +static bool cdc_zero(target_ulong *psw)
> +{
> +    int cdc = *psw & MASK_PSW_CDC;
> +    /* Returns TRUE if PSW.CDC.COUNT == 0 or if PSW.CDC ==
> +       7'b1111111, otherwise returns FALSE. */
> +    if (cdc == 0x7f) {
> +        return true;
> +    }
> +    /* find CDC.COUNT */
> +    if (((1 << (6 - clo32(*psw & MASK_PSW_CDC))) - 1) == 0) {
> +        return true;
> +    }
> +
> +    return false;
> +}

You've misunderstood me wrt clo.  As written here, it'll always return 0, since
the value you're passing is zero-extended to 32 bits.

Something like

  int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
  int mask = (1u << (7 - lo)) - 1;
  int count = *psw & mask;
  return count == 0;

> +static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
> +{
> +    TCGv sat_neg = tcg_const_i32(low);
> +    TCGv temp = tcg_const_i32(up);
> +
> +    /* sat_neg = (arg < low ) ? low : arg; */
> +    tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, arg, sat_neg);
> +
> +    /* ret = (sat_neg > up ) ? up  : sat_neg; */
> +    tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
> +
> +    tcg_temp_free(sat_neg);

Forgot to free temp.

> +    case OPC2_16_SR_RSUB:
> +        tcg_gen_subfi_tl(cpu_gpr_d[r1], 0, cpu_gpr_d[r1]);
> +        break;

tcg_gen_neg_tl.


r~