Re: [PATCH 0/3] Use dedicated RI/XI exceptions for MIPSR5 cores

[David Daney <ddaney.cavm@gmail.com>]

On 07/15/2014 06:09 AM, Markos Chandras wrote:
> Hi,
>
> This patchset adds support for unique RI/XI exceptions. This feature has
> been added in MIPSr5. Using this feature, we reduce the time it takes
> to deal with a TLB exception caused by the RI/XI bits since the TLB load
> handler is skipped and we use the tlb_do_page_failt_0 path directly.
>
> This patch depends on the Hardware Page Table Walker (HTW) patchset
> http://www.linux-mips.org/archives/linux-mips/2014-07/msg00195.html

They are unrelated features, why the dependency?


>
> Leonid Yegoshin (3):
>    MIPS: Add new option for unique RI/XI exceptions
>    MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions
>    MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions

There is code in mm/fault.c that generates the SIGSEGV for the RI/XI 
violations.  If we are using the dedicated RI/XI exception vectors, that 
code no longer has to make assumptions about what caused the exception.

I wonder if this should be reworked so that we don't make any 
assumptions about the cause of the exception.

David Daney


>
>   arch/mips/include/asm/cpu-features.h | 3 +++
>   arch/mips/include/asm/cpu.h          | 1 +
>   arch/mips/include/asm/mipsregs.h     | 1 +
>   arch/mips/kernel/cpu-probe.c         | 9 +++++++++
>   arch/mips/kernel/traps.c             | 7 +++++++
>   arch/mips/mm/tlbex.c                 | 4 ++--
>   6 files changed, 23 insertions(+), 2 deletions(-)
>