diff for duplicates of <53CA8D95.8010108@ti.com> diff --git a/a/1.txt b/N1/1.txt index f0c9fad..7b2d8f0 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -65,7 +65,7 @@ Does that make sense ? > #address-cells = <1>; > #size-cells = <0>; > -> cpu0: cpu@0 { +> cpu0: cpu at 0 { > compatible = "arm,cortex-a15"; > reg = <0>; > next-level-cache = <&L2>; @@ -78,7 +78,7 @@ Does that make sense ? > clock-latency = <61036>; /* two CLK32 periods */ > }; > -> cpu1: cpu@1 { +> cpu1: cpu at 1 { > compatible = "arm,cortex-a15"; > reg = <1>; > next-level-cache = <&L2>; @@ -91,7 +91,7 @@ Does that make sense ? > #address-cells = <1>; > #size-cells = <0>; > -> cpu0: cpu@0 { +> cpu0: cpu at 0 { > compatible = "arm,cortex-a15"; > reg = <0>; > next-level-cache = <&L2>; @@ -104,7 +104,7 @@ Does that make sense ? > clock-latency = <61036>; /* two CLK32 periods */ > }; > -> cpu1: cpu@1 { +> cpu1: cpu at 1 { > compatible = "arm,cortex-a15"; > reg = <1>; > next-level-cache = <&L2>; @@ -125,7 +125,7 @@ Does that make sense ? > #address-cells = <1>; > #size-cells = <0>; > -> cpu0: cpu@0 { +> cpu0: cpu at 0 { > compatible = "arm,cortex-a15"; > reg = <0>; > next-level-cache = <&L2>; @@ -138,14 +138,14 @@ Does that make sense ? > clock-latency = <61036>; /* two CLK32 periods */ > }; > -> cpu1: cpu@1 { +> cpu1: cpu at 1 { > compatible = "arm,cortex-a15"; > reg = <1>; > next-level-cache = <&L2>; > clock-master = <&cpu0>; > }; > -> cpu2: cpu@100 { +> cpu2: cpu at 100 { > compatible = "arm,cortex-a7"; > reg = <100>; > next-level-cache = <&L2>; @@ -158,7 +158,7 @@ Does that make sense ? > clock-latency = <61036>; /* two CLK32 periods */ > }; > -> cpu3: cpu@101 { +> cpu3: cpu at 101 { > compatible = "arm,cortex-a7"; > reg = <101>; > next-level-cache = <&L2>; diff --git a/a/content_digest b/N1/content_digest index def6ee6..fa6a3b6 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,25 +3,10 @@ "ref\0CAKohpo=MmoALOHg-=7cf0jm=OJO57TWQZQXqkRwhRwU-DGPMmA@mail.gmail.com\0" "ref\0CAOesGMhuNzVtUkaUjF+JjNgHcgf08WiM0DG-kzwtcyUxkK_zow@mail.gmail.com\0" "ref\0CAKohpokLqrydV3b=innvOWrW9ijXtZwPKdT5Ew65cjMxsY2Mvw@mail.gmail.com\0" - "From\0Santosh Shilimkar <santosh.shilimkar@ti.com>\0" - "Subject\0Re: [RFC] cpufreq: Add bindings for CPU clock sharing topology\0" + "From\0santosh.shilimkar@ti.com (Santosh Shilimkar)\0" + "Subject\0[RFC] cpufreq: Add bindings for CPU clock sharing topology\0" "Date\0Sat, 19 Jul 2014 11:24:05 -0400\0" - "To\0Viresh Kumar <viresh.kumar@linaro.org>" - Olof Johansson <olof@lixom.net> - " Rob Herring <rob.herring@linaro.org>\0" - "Cc\0Rafael J. Wysocki <rjw@rjwysocki.net>" - Mike Turquette <mike.turquette@linaro.org> - Grant Likely <grant.likely@linaro.org> - linaro-kernel@lists.linaro.org <linaro-kernel@lists.linaro.org> - Nishanth Menon <nm@ti.com> - Sudeep Holla <Sudeep.Holla@arm.com> - Stephen Boyd <sboyd@codeaurora.org> - linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> - linux-pm@vger.kernel.org <linux-pm@vger.kernel.org> - devicetree@vger.kernel.org <devicetree@vger.kernel.org> - Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com> - Arvind Chauhan <arvind.chauhan@arm.com> - " Arnd Bergmann <arnd.bergmann@linaro.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Viresh,\n" @@ -91,7 +76,7 @@ "> #address-cells = <1>;\n" "> #size-cells = <0>;\n" "> \n" - "> cpu0: cpu@0 {\n" + "> cpu0: cpu at 0 {\n" "> compatible = \"arm,cortex-a15\";\n" "> reg = <0>;\n" "> next-level-cache = <&L2>;\n" @@ -104,7 +89,7 @@ "> clock-latency = <61036>; /* two CLK32 periods */\n" "> };\n" "> \n" - "> cpu1: cpu@1 {\n" + "> cpu1: cpu at 1 {\n" "> compatible = \"arm,cortex-a15\";\n" "> reg = <1>;\n" "> next-level-cache = <&L2>;\n" @@ -117,7 +102,7 @@ "> #address-cells = <1>;\n" "> #size-cells = <0>;\n" "> \n" - "> cpu0: cpu@0 {\n" + "> cpu0: cpu at 0 {\n" "> compatible = \"arm,cortex-a15\";\n" "> reg = <0>;\n" "> next-level-cache = <&L2>;\n" @@ -130,7 +115,7 @@ "> clock-latency = <61036>; /* two CLK32 periods */\n" "> };\n" "> \n" - "> cpu1: cpu@1 {\n" + "> cpu1: cpu at 1 {\n" "> compatible = \"arm,cortex-a15\";\n" "> reg = <1>;\n" "> next-level-cache = <&L2>;\n" @@ -151,7 +136,7 @@ "> #address-cells = <1>;\n" "> #size-cells = <0>;\n" "> \n" - "> cpu0: cpu@0 {\n" + "> cpu0: cpu at 0 {\n" "> compatible = \"arm,cortex-a15\";\n" "> reg = <0>;\n" "> next-level-cache = <&L2>;\n" @@ -164,14 +149,14 @@ "> clock-latency = <61036>; /* two CLK32 periods */\n" "> };\n" "> \n" - "> cpu1: cpu@1 {\n" + "> cpu1: cpu at 1 {\n" "> compatible = \"arm,cortex-a15\";\n" "> reg = <1>;\n" "> next-level-cache = <&L2>;\n" "> clock-master = <&cpu0>;\n" "> };\n" "> \n" - "> cpu2: cpu@100 {\n" + "> cpu2: cpu at 100 {\n" "> compatible = \"arm,cortex-a7\";\n" "> reg = <100>;\n" "> next-level-cache = <&L2>;\n" @@ -184,7 +169,7 @@ "> clock-latency = <61036>; /* two CLK32 periods */\n" "> };\n" "> \n" - "> cpu3: cpu@101 {\n" + "> cpu3: cpu at 101 {\n" "> compatible = \"arm,cortex-a7\";\n" "> reg = <101>;\n" "> next-level-cache = <&L2>;\n" @@ -193,4 +178,4 @@ "> };\n" > -dc21f190743db1c32e07b72fd10823aa33f151980e186cd05724d7e4b285c69a +2bf49fa77d9b723b0132ab32a7fdb412da7ba0fc6a0a23d359a542342e96a55f
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.