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[216.31.211.11]) by mx.google.com with ESMTPSA id da7sm28489264pdb.4.2014.08.04.15.54.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Aug 2014 15:54:59 -0700 (PDT) Message-ID: <53E00F39.7@gmail.com> Date: Mon, 04 Aug 2014 15:54:49 -0700 From: Florian Fainelli User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.0 MIME-Version: 1.0 To: Markos Chandras , linux-mips@linux-mips.org Subject: Re: [PATCH 3/4] MIPS: cpu-probe: Set the write-combine CCA value on per core basis References: <1405677093-22591-1-git-send-email-markos.chandras@imgtec.com> <1405677093-22591-4-git-send-email-markos.chandras@imgtec.com> In-Reply-To: <1405677093-22591-4-git-send-email-markos.chandras@imgtec.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 41878 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: f.fainelli@gmail.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Hi Markos, On 07/18/2014 02:51 AM, Markos Chandras wrote: > Different cores use different CCA values to achieve write-combine > memory writes. For cores that do not support write-combine we > set the default value to CCA:2 (uncached, non-coherent) which is the > default value as set by the kernel. > > Signed-off-by: Markos Chandras > --- [snip] break; > @@ -765,67 +767,83 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) > > static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) > { > + c->writecombine = _CACHE_UNCACHED_ACCELERATED; Why do we set this writecombine setting by default, when later we are going to override writecombine on a per-cpu basic. In the end, we have the following: cpu_probe() c->writecombine = _CACHE_UNCACHED; cpu_probe_mips() c->writecombine = _CACHE_UNCACHED_ACCELERATED: ... per-cpu case ... c->writecombine = _CACHE_UNCACHED; Can't we just eliminate the various assignments in cpu_probe_mips() and only override c->writecombine if _CACHE_UNCACHED is not suitable? > switch (c->processor_id & PRID_IMP_MASK) { > case PRID_IMP_4KC: > c->cputype = CPU_4KC; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS 4Kc"; > break; > case PRID_IMP_4KEC: > case PRID_IMP_4KECR2: > c->cputype = CPU_4KEC; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS 4KEc"; > break; > case PRID_IMP_4KSC: > case PRID_IMP_4KSD: > c->cputype = CPU_4KSC; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS 4KSc"; > break; > case PRID_IMP_5KC: > c->cputype = CPU_5KC; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS 5Kc"; > break; > case PRID_IMP_5KE: > c->cputype = CPU_5KE; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS 5KE"; > break; > case PRID_IMP_20KC: > c->cputype = CPU_20KC; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS 20Kc"; > break; > case PRID_IMP_24K: > c->cputype = CPU_24K; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS 24Kc"; > break; > case PRID_IMP_24KE: > c->cputype = CPU_24K; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS 24KEc"; > break; > case PRID_IMP_25KF: > c->cputype = CPU_25KF; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS 25Kc"; > break; > case PRID_IMP_34K: > c->cputype = CPU_34K; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS 34Kc"; > break; > case PRID_IMP_74K: > c->cputype = CPU_74K; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS 74Kc"; > break; > case PRID_IMP_M14KC: > c->cputype = CPU_M14KC; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS M14Kc"; > break; > case PRID_IMP_M14KEC: > c->cputype = CPU_M14KEC; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS M14KEc"; > break; > case PRID_IMP_1004K: > c->cputype = CPU_1004K; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS 1004Kc"; > break; > case PRID_IMP_1074K: > c->cputype = CPU_1074K; > + c->writecombine = _CACHE_UNCACHED; > __cpu_name[cpu] = "MIPS 1074Kc"; > break; > case PRID_IMP_INTERAPTIV_UP: > @@ -899,6 +917,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) > { > decode_configs(c); > > + c->writecombine = _CACHE_UNCACHED_ACCELERATED; > switch (c->processor_id & PRID_IMP_MASK) { > case PRID_IMP_SB1: > c->cputype = CPU_SB1; > @@ -1030,6 +1049,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) > switch (c->processor_id & PRID_IMP_MASK) { > case PRID_IMP_JZRISC: > c->cputype = CPU_JZRISC; > + c->writecombine = _CACHE_UNCACHED_ACCELERATED; > __cpu_name[cpu] = "Ingenic JZRISC"; > break; > default: > @@ -1136,6 +1156,7 @@ void cpu_probe(void) > c->processor_id = PRID_IMP_UNKNOWN; > c->fpu_id = FPIR_IMP_NONE; > c->cputype = CPU_UNKNOWN; > + c->writecombine = _CACHE_UNCACHED; > > c->processor_id = read_c0_prid(); > switch (c->processor_id & PRID_COMP_MASK) { >