* [RFC 0/2] Add test to verify BDW workarounds @ 2014-08-08 9:54 arun.siluvery 2014-08-08 9:54 ` [RFC 1/2] tools/null_state_render: Add BDW workarounds to golden render state arun.siluvery 2014-08-08 9:54 ` [RFC 2/2] igt/gem_workarounds: igt to test workaround registers arun.siluvery 0 siblings, 2 replies; 6+ messages in thread From: arun.siluvery @ 2014-08-08 9:54 UTC (permalink / raw) To: intel-gfx From: Arun Siluvery <arun.siluvery@linux.intel.com> Currently in BDW workarounds are initialized in init_clock_gating() but some of them are lost followed by a gpu reset. The solution is to apply them in golden render state which keeps them valid when starting with an uninitialized state. First patch adds workaround registers to golden render state. This patch uses functions which are part two other patches, one of which is not yet sent for upstream [2]. [1] https://www.mail-archive.com/intel-gfx@lists.freedesktop.org/msg43044.html [2] From cc8f2f657c44d7c017e70e1af11b4513358b6a0a Mon Sep 17 00:00:00 2001 From: Deepak S <deepak.s@linux.intel.com> Date: Sat, 2 Aug 2014 20:05:07 +0530 Subject: [PATCH 2/3] tools/null_state_render: Add ROW CHICKEN BIT Registers to golden render state As per, latest Bspec, some of the RenderCS registers are expected to be added in context. We achive this by adding the registers Golden render state. Signed-off-by: Deepak S <deepak.s@linux.intel.com> Second patch adds a simple test which captures workaround register data before and after a gpu reset and compares them. Suspend/Resume is currently not working hence it is not tested. The test uses intel_reg_read() to read register data but I observed that this value is different from the one compared to using I915_READ() from within the driver. e.g., in case of CACHE_MODE_1 with WA applied it should be 0x01C0. intel_reg_read() gives 0x0180 whereas with I915_READ() it is 0x01C0. Arun Siluvery (2): tools/null_state_render: Add BDW workarounds to golden render state igt/gem_workarounds: igt to test workaround registers lib/intel_reg.h | 30 ++++ tests/Makefile.sources | 1 + tests/gem_workarounds.c | 211 ++++++++++++++++++++++++++ tools/null_state_gen/intel_renderstate_gen8.c | 37 +++++ 4 files changed, 279 insertions(+) create mode 100644 tests/gem_workarounds.c -- 2.0.4 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [RFC 1/2] tools/null_state_render: Add BDW workarounds to golden render state 2014-08-08 9:54 [RFC 0/2] Add test to verify BDW workarounds arun.siluvery @ 2014-08-08 9:54 ` arun.siluvery 2014-08-08 9:54 ` [RFC 2/2] igt/gem_workarounds: igt to test workaround registers arun.siluvery 1 sibling, 0 replies; 6+ messages in thread From: arun.siluvery @ 2014-08-08 9:54 UTC (permalink / raw) To: intel-gfx From: Arun Siluvery <arun.siluvery@linux.intel.com> Some workaround registers are part of register state context and they are restored with every context switch so initializing them in golden render state ensures that they are applied even when we start with an uninitialized context or during hw initialization followed by a reset. Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- lib/intel_reg.h | 22 ++++++++++++++++ tools/null_state_gen/intel_renderstate_gen8.c | 37 +++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/lib/intel_reg.h b/lib/intel_reg.h index 4afec45..86175bb 100644 --- a/lib/intel_reg.h +++ b/lib/intel_reg.h @@ -3606,4 +3606,26 @@ typedef enum { #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 #define DOP_CLOCK_GATING_DISABLE (1<<0) +#define HALF_SLICE_CHICKEN3 0xe184 +#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) +#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) + +#define GEN7_HALF_SLICE_CHICKEN1 0xe100 +#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) + +#define COMMON_SLICE_CHICKEN2 0x7014 +# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) + +/* GEN8 chicken */ +#define HDC_CHICKEN0 0x7300 +#define HDC_FORCE_NON_COHERENT (1<<4) + +#define GEN7_CACHE_MODE_1 0x7004 /* IVB+ */ +#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) + +#define GEN7_GT_MODE 0x7008 +#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) +#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) +#define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16) + #endif /* _I810_REG_H */ diff --git a/tools/null_state_gen/intel_renderstate_gen8.c b/tools/null_state_gen/intel_renderstate_gen8.c index 14690d2..a8143db 100644 --- a/tools/null_state_gen/intel_renderstate_gen8.c +++ b/tools/null_state_gen/intel_renderstate_gen8.c @@ -703,6 +703,43 @@ static void gen8_emit_workarounds(struct intel_batchbuffer *batch) /* WaDisableDopClockGating:bdw May not be needed for production */ gen8_emit_write(batch, GEN7_ROW_CHICKEN2, _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); + + /* + * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for + * pre-production hardware + */ + gen8_emit_write(batch, HALF_SLICE_CHICKEN3, + _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS + | GEN8_SAMPLER_POWER_BYPASS_DIS)); + + gen8_emit_write(batch, GEN7_HALF_SLICE_CHICKEN1, + _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); + + gen8_emit_write(batch, COMMON_SLICE_CHICKEN2, + _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); + + /* Use Force Non-Coherent whenever executing a 3D context. This is a + * workaround for for a possible hang in the unlikely event a TLB + * invalidation occurs during a PSD flush. + */ + gen8_emit_write(batch, HDC_CHICKEN0, + _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT)); + + /* Wa4x4STCOptimizationDisable:bdw */ + gen8_emit_write(batch, GEN7_CACHE_MODE_1, + _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); + + /* + * BSpec recommends 8x4 when MSAA is used, + * however in practice 16x4 seems fastest. + * + * Note that PS/WM thread counts depend on the WIZ hashing + * disable bit, which we don't touch here, but it's good + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). + */ + gen8_emit_write(batch, GEN7_GT_MODE, + GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); + } int gen8_setup_null_render_state(struct intel_batchbuffer *batch) -- 2.0.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [RFC 2/2] igt/gem_workarounds: igt to test workaround registers 2014-08-08 9:54 [RFC 0/2] Add test to verify BDW workarounds arun.siluvery 2014-08-08 9:54 ` [RFC 1/2] tools/null_state_render: Add BDW workarounds to golden render state arun.siluvery @ 2014-08-08 9:54 ` arun.siluvery 2014-08-08 14:12 ` Daniel Vetter 1 sibling, 1 reply; 6+ messages in thread From: arun.siluvery @ 2014-08-08 9:54 UTC (permalink / raw) To: intel-gfx [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #1: Type: text/plain; charset=y, Size: 7395 bytes --] From: Arun Siluvery <arun.siluvery@linux.intel.com> Some of the workarounds are lost followed by a gpu reset, suspend/resume; this patch adds a test which captures register state before and after the test scenario. This test currently verifies only bdw workarounds. Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- lib/intel_reg.h | 8 ++ tests/Makefile.sources | 1 + tests/gem_workarounds.c | 211 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 220 insertions(+) create mode 100644 tests/gem_workarounds.c diff --git a/lib/intel_reg.h b/lib/intel_reg.h index 86175bb..d015c36 100644 --- a/lib/intel_reg.h +++ b/lib/intel_reg.h @@ -3628,4 +3628,12 @@ typedef enum { #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) #define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16) +#define GAMTARBMODE 0x04a08 +#define _3D_CHICKEN3 0x02090 +#define GAM_ECOCHK 0x4090 +#define CHICKEN_PAR1_1 0x42080 +#define GEN7_FF_THREAD_MODE 0x20a0 +#define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 +#define GEN8_UCGCTL6 0x9430 + #endif /* _I810_REG_H */ diff --git a/tests/Makefile.sources b/tests/Makefile.sources index 0eb9369..a17acd1 100644 --- a/tests/Makefile.sources +++ b/tests/Makefile.sources @@ -134,6 +134,7 @@ TESTS_progs = \ gem_unfence_active_buffers \ gem_unref_active_buffers \ gem_wait_render_timeout \ + gem_workarounds \ gen3_mixed_blits \ gen3_render_linear_blits \ gen3_render_mixed_blits \ diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c new file mode 100644 index 0000000..35d1aa7 --- /dev/null +++ b/tests/gem_workarounds.c @@ -0,0 +1,211 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Arun Siluvery <arun.siluvery@linux.intel.com> + * + */ + +#define _GNU_SOURCE +#include <stdbool.h> +#include <unistd.h> +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <fcntl.h> +#include <inttypes.h> +#include <errno.h> +#include <sys/stat.h> +#include <sys/ioctl.h> +#include <sys/mman.h> +#include <time.h> +#include <signal.h> + +#include "ioctl_wrappers.h" +#include "drmtest.h" +#include "igt_debugfs.h" +#include "igt_aux.h" +#include "intel_chipset.h" +#include "intel_io.h" + +int drm_fd; +static drm_intel_bufmgr *bufmgr; +struct intel_batchbuffer *batch; +uint32_t devid; + +enum operation { + GPU_RESET, + SUSPEND_RESUME, +}; + +struct workaround { + const char *reg_name; + uint32_t address; +}; + +static struct workaround bdw_workarounds[] = +{ + { "GEN8_ROW_CHICKEN", GEN8_ROW_CHICKEN }, + { "GEN7_ROW_CHICKEN2", GEN7_ROW_CHICKEN2 }, + { "HALF_SLICE_CHICKEN3", HALF_SLICE_CHICKEN3 }, + { "GEN7_HALF_SLICE_CHICKEN1", GEN7_HALF_SLICE_CHICKEN1 }, + { "COMMON_SLICE_CHICKEN2", COMMON_SLICE_CHICKEN2 }, + { "HDC_CHICKEN0", HDC_CHICKEN0 }, + { "GEN7_CACHE_MODE_1", GEN7_CACHE_MODE_1 }, + { "GEN7_GT_MODE", GEN7_GT_MODE }, + { "GAMTARBMODE", GAMTARBMODE }, + { "_3D_CHICKEN3", _3D_CHICKEN3 }, + { "GAM_ECOCHK", GAM_ECOCHK }, + { "CHICKEN_PAR1_1", CHICKEN_PAR1_1 }, + { "GEN7_FF_THREAD_MODE", GEN7_FF_THREAD_MODE }, + { "GEN6_RC_SLEEP_PSMI_CONTROL", GEN6_RC_SLEEP_PSMI_CONTROL }, + { "GEN8_UCGCTL6", GEN8_UCGCTL6 }, + { "NULL", 0xFFFF }, +}; + +static void test_hang_gpu(void) +{ + int retry_count = 30; + enum stop_ring_flags flags; + struct drm_i915_gem_execbuffer2 execbuf; + struct drm_i915_gem_exec_object2 gem_exec; + uint32_t b[2] = {MI_BATCH_BUFFER_END}; + + igt_assert(retry_count); + igt_set_stop_rings(STOP_RING_DEFAULTS); + + memset(&gem_exec, 0, sizeof(gem_exec)); + gem_exec.handle = gem_create(drm_fd, 4096); + gem_write(drm_fd, gem_exec.handle, 0, b, sizeof(b)); + + memset(&execbuf, 0, sizeof(execbuf)); + execbuf.buffers_ptr = (uintptr_t)&gem_exec; + execbuf.buffer_count = 1; + execbuf.batch_len = sizeof(b); + + drmIoctl(drm_fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf); + + while(retry_count--) { + flags = igt_get_stop_rings(); + if (flags == 0) + break; + printf("gpu hang not yet cleared, retries left %d\n", retry_count); + sleep(1); + } + + flags = igt_get_stop_rings(); + if (flags) + igt_set_stop_rings(STOP_RING_NONE); +} + +static void test_suspend_resume(void) +{ + printf("Suspending the device ...\n"); + igt_system_suspend_autoresume(); +} + +static void capture_wa_state(struct workaround *wa_regs, int num_wa, + unsigned int *reg_values) +{ + int i; + + igt_assert(reg_values); + intel_register_access_init(intel_get_pci_device(), 0); + + for (i = 0; i < num_wa; ++i) + reg_values[i] = intel_register_read(wa_regs[i].address); + + intel_register_access_fini(); +} + +static void check_workarounds(struct workaround *wa, enum operation op) +{ + int i; + int num_wa = 0; + unsigned int *before; + unsigned int *after; + bool fail = false; + + while(wa[num_wa].address != 0xFFFF) + num_wa++; + + igt_assert(num_wa); + + before = malloc(num_wa * sizeof(*before)); + memset(before, 0x00, num_wa * sizeof(*before)); + capture_wa_state(wa, num_wa, before); + + switch (op) { + case GPU_RESET: + test_hang_gpu(); + break; + + case SUSPEND_RESUME: + test_suspend_resume(); + break; + + default: + fail = true; + goto out; + } + + after = malloc(num_wa * sizeof(*after)); + memset(after, 0x00, num_wa * sizeof(*after)); + capture_wa_state(wa, num_wa, after); + + for (i = 0; i < num_wa; ++i) { + if (before[i] != after[i]) { + fail = true; + printf("%s workaround failed, before: 0x%08X, after: 0x%08X\n", + wa[i].reg_name, before[i], after[i]); + } + } + + free(after); + +out: + free(before); + + igt_assert(fail == false); +} + +int main(int argc, char **argv) +{ + igt_subtest_init(argc, argv); + + igt_fixture { + drm_fd = drm_open_any(); + + bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096); + devid = intel_get_drm_devid(drm_fd); + batch = intel_batchbuffer_alloc(bufmgr, devid); + } + + igt_subtest("check-workaround-data-after-reset") { + if (IS_BROADWELL(devid)) + check_workarounds(&bdw_workarounds[0], GPU_RESET); + } + + + close(drm_fd); + igt_exit(); +} -- 2.0.4 [-- Attachment #2: Type: text/plain, Size: 159 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [RFC 2/2] igt/gem_workarounds: igt to test workaround registers 2014-08-08 9:54 ` [RFC 2/2] igt/gem_workarounds: igt to test workaround registers arun.siluvery @ 2014-08-08 14:12 ` Daniel Vetter 2014-08-08 16:39 ` Siluvery, Arun 0 siblings, 1 reply; 6+ messages in thread From: Daniel Vetter @ 2014-08-08 14:12 UTC (permalink / raw) To: arun.siluvery; +Cc: intel-gfx On Fri, Aug 08, 2014 at 10:54:56AM +0100, arun.siluvery@linux.intel.com wrote: > From: Arun Siluvery <arun.siluvery@linux.intel.com> > > Some of the workarounds are lost followed by a gpu reset, suspend/resume; > this patch adds a test which captures register state before and after > the test scenario. > > This test currently verifies only bdw workarounds. > > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Some comments below. > --- > lib/intel_reg.h | 8 ++ > tests/Makefile.sources | 1 + > tests/gem_workarounds.c | 211 ++++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 220 insertions(+) > create mode 100644 tests/gem_workarounds.c > > diff --git a/lib/intel_reg.h b/lib/intel_reg.h > index 86175bb..d015c36 100644 > --- a/lib/intel_reg.h > +++ b/lib/intel_reg.h > @@ -3628,4 +3628,12 @@ typedef enum { > #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) > #define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16) > > +#define GAMTARBMODE 0x04a08 > +#define _3D_CHICKEN3 0x02090 > +#define GAM_ECOCHK 0x4090 > +#define CHICKEN_PAR1_1 0x42080 > +#define GEN7_FF_THREAD_MODE 0x20a0 > +#define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 > +#define GEN8_UCGCTL6 0x9430 > + > #endif /* _I810_REG_H */ > diff --git a/tests/Makefile.sources b/tests/Makefile.sources > index 0eb9369..a17acd1 100644 > --- a/tests/Makefile.sources > +++ b/tests/Makefile.sources > @@ -134,6 +134,7 @@ TESTS_progs = \ > gem_unfence_active_buffers \ > gem_unref_active_buffers \ > gem_wait_render_timeout \ > + gem_workarounds \ > gen3_mixed_blits \ > gen3_render_linear_blits \ > gen3_render_mixed_blits \ > diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c > new file mode 100644 > index 0000000..35d1aa7 > --- /dev/null > +++ b/tests/gem_workarounds.c > @@ -0,0 +1,211 @@ > +/* > + * Copyright © 2014 Intel Corporation > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice (including the next > + * paragraph) shall be included in all copies or substantial portions of the > + * Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS > + * IN THE SOFTWARE. > + * > + * Authors: > + * Arun Siluvery <arun.siluvery@linux.intel.com> > + * > + */ > + > +#define _GNU_SOURCE > +#include <stdbool.h> > +#include <unistd.h> > +#include <stdlib.h> > +#include <stdio.h> > +#include <string.h> > +#include <fcntl.h> > +#include <inttypes.h> > +#include <errno.h> > +#include <sys/stat.h> > +#include <sys/ioctl.h> > +#include <sys/mman.h> > +#include <time.h> > +#include <signal.h> > + > +#include "ioctl_wrappers.h" > +#include "drmtest.h" > +#include "igt_debugfs.h" > +#include "igt_aux.h" > +#include "intel_chipset.h" > +#include "intel_io.h" > + > +int drm_fd; > +static drm_intel_bufmgr *bufmgr; > +struct intel_batchbuffer *batch; > +uint32_t devid; > + > +enum operation { > + GPU_RESET, > + SUSPEND_RESUME, The suspend test doesn't seem to be wire up ... Also I think it would be worth to have a module-reload version here too. > +}; > + > +struct workaround { > + const char *reg_name; > + uint32_t address; > +}; > + > +static struct workaround bdw_workarounds[] = > +{ > + { "GEN8_ROW_CHICKEN", GEN8_ROW_CHICKEN }, > + { "GEN7_ROW_CHICKEN2", GEN7_ROW_CHICKEN2 }, > + { "HALF_SLICE_CHICKEN3", HALF_SLICE_CHICKEN3 }, > + { "GEN7_HALF_SLICE_CHICKEN1", GEN7_HALF_SLICE_CHICKEN1 }, > + { "COMMON_SLICE_CHICKEN2", COMMON_SLICE_CHICKEN2 }, > + { "HDC_CHICKEN0", HDC_CHICKEN0 }, > + { "GEN7_CACHE_MODE_1", GEN7_CACHE_MODE_1 }, > + { "GEN7_GT_MODE", GEN7_GT_MODE }, > + { "GAMTARBMODE", GAMTARBMODE }, > + { "_3D_CHICKEN3", _3D_CHICKEN3 }, > + { "GAM_ECOCHK", GAM_ECOCHK }, > + { "CHICKEN_PAR1_1", CHICKEN_PAR1_1 }, > + { "GEN7_FF_THREAD_MODE", GEN7_FF_THREAD_MODE }, > + { "GEN6_RC_SLEEP_PSMI_CONTROL", GEN6_RC_SLEEP_PSMI_CONTROL }, > + { "GEN8_UCGCTL6", GEN8_UCGCTL6 }, > + { "NULL", 0xFFFF }, > +}; Crazy idea I've just had to validate that all the w/a table here is up-to-date with the one in the kernel: - We create a special WA_REG macro in the kernel which we use to wrap all registers used in workarounds at the specific use-site (i.e. not in the header). So I951_WRITE(WA_REG(GEN8_ROW_CHICKEN), ....); - That macro then adds the register to a table which we can dump through debugs with a file called intel_wa_registers. This happens at runtime. This is important since a static list over all platforms might included registers which hang some platforms when we read them. - A special subtest in this test here compares the kernel-provided list with the one supplied here and makes sure that all the w/a in the kernel list are in the test list, too. Or we just ditch the test list here completely, but that might not work for special cases where we only need to check some masks ... Opinions on this? Would this help with maintaining this testcase and ensuring that it is always up-to-date with the kernel w/a list? I really want to make sure we get this right, there's been way too many cases where w/a settings have been lost over resume, runtime pm, ctx switches ... > + > +static void test_hang_gpu(void) > +{ > + int retry_count = 30; > + enum stop_ring_flags flags; > + struct drm_i915_gem_execbuffer2 execbuf; > + struct drm_i915_gem_exec_object2 gem_exec; > + uint32_t b[2] = {MI_BATCH_BUFFER_END}; > + > + igt_assert(retry_count); > + igt_set_stop_rings(STOP_RING_DEFAULTS); > + > + memset(&gem_exec, 0, sizeof(gem_exec)); > + gem_exec.handle = gem_create(drm_fd, 4096); > + gem_write(drm_fd, gem_exec.handle, 0, b, sizeof(b)); > + > + memset(&execbuf, 0, sizeof(execbuf)); > + execbuf.buffers_ptr = (uintptr_t)&gem_exec; > + execbuf.buffer_count = 1; > + execbuf.batch_len = sizeof(b); > + > + drmIoctl(drm_fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf); > + > + while(retry_count--) { > + flags = igt_get_stop_rings(); > + if (flags == 0) > + break; > + printf("gpu hang not yet cleared, retries left %d\n", retry_count); > + sleep(1); > + } > + > + flags = igt_get_stop_rings(); > + if (flags) > + igt_set_stop_rings(STOP_RING_NONE); > +} > + > +static void test_suspend_resume(void) > +{ > + printf("Suspending the device ...\n"); > + igt_system_suspend_autoresume(); > +} > + > +static void capture_wa_state(struct workaround *wa_regs, int num_wa, > + unsigned int *reg_values) > +{ > + int i; > + > + igt_assert(reg_values); > + intel_register_access_init(intel_get_pci_device(), 0); > + > + for (i = 0; i < num_wa; ++i) > + reg_values[i] = intel_register_read(wa_regs[i].address); > + > + intel_register_access_fini(); > +} > + > +static void check_workarounds(struct workaround *wa, enum operation op) > +{ > + int i; > + int num_wa = 0; > + unsigned int *before; > + unsigned int *after; > + bool fail = false; > + > + while(wa[num_wa].address != 0xFFFF) > + num_wa++; > + > + igt_assert(num_wa); > + > + before = malloc(num_wa * sizeof(*before)); > + memset(before, 0x00, num_wa * sizeof(*before)); > + capture_wa_state(wa, num_wa, before); > + > + switch (op) { > + case GPU_RESET: > + test_hang_gpu(); > + break; > + > + case SUSPEND_RESUME: > + test_suspend_resume(); > + break; > + > + default: > + fail = true; > + goto out; > + } > + > + after = malloc(num_wa * sizeof(*after)); > + memset(after, 0x00, num_wa * sizeof(*after)); > + capture_wa_state(wa, num_wa, after); > + > + for (i = 0; i < num_wa; ++i) { > + if (before[i] != after[i]) { > + fail = true; > + printf("%s workaround failed, before: 0x%08X, after: 0x%08X\n", > + wa[i].reg_name, before[i], after[i]); > + } > + } > + > + free(after); > + > +out: > + free(before); > + > + igt_assert(fail == false); > +} > + > +int main(int argc, char **argv) > +{ > + igt_subtest_init(argc, argv); > + > + igt_fixture { > + drm_fd = drm_open_any(); > + > + bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096); > + devid = intel_get_drm_devid(drm_fd); > + batch = intel_batchbuffer_alloc(bufmgr, devid); > + } > + > + igt_subtest("check-workaround-data-after-reset") { > + if (IS_BROADWELL(devid)) The logic here should be switched around, or at least if you don't have a w/a table for a given platform we should skip the test. And tbh for anything gen8+ we should fail it so that someone knows there's still work to to. > + check_workarounds(&bdw_workarounds[0], GPU_RESET); A simple else igt_skip_on("No w/a table found!\"); here should do the trick. > + } > + > + > + close(drm_fd); > + igt_exit(); > +} > -- > 2.0.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [RFC 2/2] igt/gem_workarounds: igt to test workaround registers 2014-08-08 14:12 ` Daniel Vetter @ 2014-08-08 16:39 ` Siluvery, Arun 2014-08-08 17:00 ` Daniel Vetter 0 siblings, 1 reply; 6+ messages in thread From: Siluvery, Arun @ 2014-08-08 16:39 UTC (permalink / raw) To: Daniel Vetter; +Cc: intel-gfx On 08/08/2014 15:12, Daniel Vetter wrote: > On Fri, Aug 08, 2014 at 10:54:56AM +0100, arun.siluvery@linux.intel.com wrote: >> From: Arun Siluvery <arun.siluvery@linux.intel.com> >> >> Some of the workarounds are lost followed by a gpu reset, suspend/resume; >> this patch adds a test which captures register state before and after >> the test scenario. >> >> This test currently verifies only bdw workarounds. >> >> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > > Some comments below. > >> --- >> lib/intel_reg.h | 8 ++ >> tests/Makefile.sources | 1 + >> tests/gem_workarounds.c | 211 ++++++++++++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 220 insertions(+) >> create mode 100644 tests/gem_workarounds.c >> >> diff --git a/lib/intel_reg.h b/lib/intel_reg.h >> index 86175bb..d015c36 100644 >> --- a/lib/intel_reg.h >> +++ b/lib/intel_reg.h >> @@ -3628,4 +3628,12 @@ typedef enum { >> #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) >> #define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16) >> >> +#define GAMTARBMODE 0x04a08 >> +#define _3D_CHICKEN3 0x02090 >> +#define GAM_ECOCHK 0x4090 >> +#define CHICKEN_PAR1_1 0x42080 >> +#define GEN7_FF_THREAD_MODE 0x20a0 >> +#define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 >> +#define GEN8_UCGCTL6 0x9430 >> + >> #endif /* _I810_REG_H */ >> diff --git a/tests/Makefile.sources b/tests/Makefile.sources >> index 0eb9369..a17acd1 100644 >> --- a/tests/Makefile.sources >> +++ b/tests/Makefile.sources >> @@ -134,6 +134,7 @@ TESTS_progs = \ >> gem_unfence_active_buffers \ >> gem_unref_active_buffers \ >> gem_wait_render_timeout \ >> + gem_workarounds \ >> gen3_mixed_blits \ >> gen3_render_linear_blits \ >> gen3_render_mixed_blits \ >> diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c >> new file mode 100644 >> index 0000000..35d1aa7 >> --- /dev/null >> +++ b/tests/gem_workarounds.c >> @@ -0,0 +1,211 @@ >> +/* >> + * Copyright © 2014 Intel Corporation >> + * >> + * Permission is hereby granted, free of charge, to any person obtaining a >> + * copy of this software and associated documentation files (the "Software"), >> + * to deal in the Software without restriction, including without limitation >> + * the rights to use, copy, modify, merge, publish, distribute, sublicense, >> + * and/or sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following conditions: >> + * >> + * The above copyright notice and this permission notice (including the next >> + * paragraph) shall be included in all copies or substantial portions of the >> + * Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS >> + * IN THE SOFTWARE. >> + * >> + * Authors: >> + * Arun Siluvery <arun.siluvery@linux.intel.com> >> + * >> + */ >> + >> +#define _GNU_SOURCE >> +#include <stdbool.h> >> +#include <unistd.h> >> +#include <stdlib.h> >> +#include <stdio.h> >> +#include <string.h> >> +#include <fcntl.h> >> +#include <inttypes.h> >> +#include <errno.h> >> +#include <sys/stat.h> >> +#include <sys/ioctl.h> >> +#include <sys/mman.h> >> +#include <time.h> >> +#include <signal.h> >> + >> +#include "ioctl_wrappers.h" >> +#include "drmtest.h" >> +#include "igt_debugfs.h" >> +#include "igt_aux.h" >> +#include "intel_chipset.h" >> +#include "intel_io.h" >> + >> +int drm_fd; >> +static drm_intel_bufmgr *bufmgr; >> +struct intel_batchbuffer *batch; >> +uint32_t devid; >> + >> +enum operation { >> + GPU_RESET, >> + SUSPEND_RESUME, > > The suspend test doesn't seem to be wire up ... > > Also I think it would be worth to have a module-reload version here too. > Suspend/Resume is not working; device is not resuming even after the timer is elapsed. Do we know suspend/resume works correctly on nightly? >> +}; >> + >> +struct workaround { >> + const char *reg_name; >> + uint32_t address; >> +}; >> + >> +static struct workaround bdw_workarounds[] = >> +{ >> + { "GEN8_ROW_CHICKEN", GEN8_ROW_CHICKEN }, >> + { "GEN7_ROW_CHICKEN2", GEN7_ROW_CHICKEN2 }, >> + { "HALF_SLICE_CHICKEN3", HALF_SLICE_CHICKEN3 }, >> + { "GEN7_HALF_SLICE_CHICKEN1", GEN7_HALF_SLICE_CHICKEN1 }, >> + { "COMMON_SLICE_CHICKEN2", COMMON_SLICE_CHICKEN2 }, >> + { "HDC_CHICKEN0", HDC_CHICKEN0 }, >> + { "GEN7_CACHE_MODE_1", GEN7_CACHE_MODE_1 }, >> + { "GEN7_GT_MODE", GEN7_GT_MODE }, >> + { "GAMTARBMODE", GAMTARBMODE }, >> + { "_3D_CHICKEN3", _3D_CHICKEN3 }, >> + { "GAM_ECOCHK", GAM_ECOCHK }, >> + { "CHICKEN_PAR1_1", CHICKEN_PAR1_1 }, >> + { "GEN7_FF_THREAD_MODE", GEN7_FF_THREAD_MODE }, >> + { "GEN6_RC_SLEEP_PSMI_CONTROL", GEN6_RC_SLEEP_PSMI_CONTROL }, >> + { "GEN8_UCGCTL6", GEN8_UCGCTL6 }, >> + { "NULL", 0xFFFF }, >> +}; > > Crazy idea I've just had to validate that all the w/a table here is > up-to-date with the one in the kernel: > > - We create a special WA_REG macro in the kernel which we use to wrap all > registers used in workarounds at the specific use-site (i.e. not in the > header). So > > I951_WRITE(WA_REG(GEN8_ROW_CHICKEN), ....); > > - That macro then adds the register to a table which we can dump through > debugs with a file called intel_wa_registers. This happens at runtime. > This is important since a static list over all platforms might included > registers which hang some platforms when we read them. > > - A special subtest in this test here compares the kernel-provided list > with the one supplied here and makes sure that all the w/a in the kernel > list are in the test list, too. Or we just ditch the test list here > completely, but that might not work for special cases where we only need > to check some masks ... > > Opinions on this? Would this help with maintaining this testcase and > ensuring that it is always up-to-date with the kernel w/a list? I really > want to make sure we get this right, there's been way too many cases where > w/a settings have been lost over resume, runtime pm, ctx switches ... > I will change the implementation to use this macro. so in this case the table is updated before each use case (reset, suspend/resume, module reload etc)? Is it not sufficient to capture the state at the beginning? my understanding is the wa state should really stay the same and we compare the current state (eg after reset) to the one at the beginning rather than the state before reset. I think it is easier to maintain if we completely remove the workaround list from igt itself, based on hardware macro can populate only those workarounds that are applicable but you mentioned that may not work for special cases, could you elaborate about these cases? regards Arun >> + >> +static void test_hang_gpu(void) >> +{ >> + int retry_count = 30; >> + enum stop_ring_flags flags; >> + struct drm_i915_gem_execbuffer2 execbuf; >> + struct drm_i915_gem_exec_object2 gem_exec; >> + uint32_t b[2] = {MI_BATCH_BUFFER_END}; >> + >> + igt_assert(retry_count); >> + igt_set_stop_rings(STOP_RING_DEFAULTS); >> + >> + memset(&gem_exec, 0, sizeof(gem_exec)); >> + gem_exec.handle = gem_create(drm_fd, 4096); >> + gem_write(drm_fd, gem_exec.handle, 0, b, sizeof(b)); >> + >> + memset(&execbuf, 0, sizeof(execbuf)); >> + execbuf.buffers_ptr = (uintptr_t)&gem_exec; >> + execbuf.buffer_count = 1; >> + execbuf.batch_len = sizeof(b); >> + >> + drmIoctl(drm_fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf); >> + >> + while(retry_count--) { >> + flags = igt_get_stop_rings(); >> + if (flags == 0) >> + break; >> + printf("gpu hang not yet cleared, retries left %d\n", retry_count); >> + sleep(1); >> + } >> + >> + flags = igt_get_stop_rings(); >> + if (flags) >> + igt_set_stop_rings(STOP_RING_NONE); >> +} >> + >> +static void test_suspend_resume(void) >> +{ >> + printf("Suspending the device ...\n"); >> + igt_system_suspend_autoresume(); >> +} >> + >> +static void capture_wa_state(struct workaround *wa_regs, int num_wa, >> + unsigned int *reg_values) >> +{ >> + int i; >> + >> + igt_assert(reg_values); >> + intel_register_access_init(intel_get_pci_device(), 0); >> + >> + for (i = 0; i < num_wa; ++i) >> + reg_values[i] = intel_register_read(wa_regs[i].address); >> + >> + intel_register_access_fini(); >> +} >> + >> +static void check_workarounds(struct workaround *wa, enum operation op) >> +{ >> + int i; >> + int num_wa = 0; >> + unsigned int *before; >> + unsigned int *after; >> + bool fail = false; >> + >> + while(wa[num_wa].address != 0xFFFF) >> + num_wa++; >> + >> + igt_assert(num_wa); >> + >> + before = malloc(num_wa * sizeof(*before)); >> + memset(before, 0x00, num_wa * sizeof(*before)); >> + capture_wa_state(wa, num_wa, before); >> + >> + switch (op) { >> + case GPU_RESET: >> + test_hang_gpu(); >> + break; >> + >> + case SUSPEND_RESUME: >> + test_suspend_resume(); >> + break; >> + >> + default: >> + fail = true; >> + goto out; >> + } >> + >> + after = malloc(num_wa * sizeof(*after)); >> + memset(after, 0x00, num_wa * sizeof(*after)); >> + capture_wa_state(wa, num_wa, after); >> + >> + for (i = 0; i < num_wa; ++i) { >> + if (before[i] != after[i]) { >> + fail = true; >> + printf("%s workaround failed, before: 0x%08X, after: 0x%08X\n", >> + wa[i].reg_name, before[i], after[i]); >> + } >> + } >> + >> + free(after); >> + >> +out: >> + free(before); >> + >> + igt_assert(fail == false); >> +} >> + >> +int main(int argc, char **argv) >> +{ >> + igt_subtest_init(argc, argv); >> + >> + igt_fixture { >> + drm_fd = drm_open_any(); >> + >> + bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096); >> + devid = intel_get_drm_devid(drm_fd); >> + batch = intel_batchbuffer_alloc(bufmgr, devid); >> + } >> + >> + igt_subtest("check-workaround-data-after-reset") { >> + if (IS_BROADWELL(devid)) > > The logic here should be switched around, or at least if you don't have a > w/a table for a given platform we should skip the test. And tbh for > anything gen8+ we should fail it so that someone knows there's still work > to to. >> + check_workarounds(&bdw_workarounds[0], GPU_RESET); > > A simple > > else > igt_skip_on("No w/a table found!\"); > > here should do the trick. > >> + } >> + >> + >> + close(drm_fd); >> + igt_exit(); >> +} >> -- >> 2.0.4 >> > >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [RFC 2/2] igt/gem_workarounds: igt to test workaround registers 2014-08-08 16:39 ` Siluvery, Arun @ 2014-08-08 17:00 ` Daniel Vetter 0 siblings, 0 replies; 6+ messages in thread From: Daniel Vetter @ 2014-08-08 17:00 UTC (permalink / raw) To: Siluvery, Arun; +Cc: intel-gfx On Fri, Aug 8, 2014 at 6:39 PM, Siluvery, Arun <arun.siluvery@linux.intel.com> wrote: >> >> The suspend test doesn't seem to be wire up ... >> >> Also I think it would be worth to have a module-reload version here too. >> > Suspend/Resume is not working; device is not resuming even after the timer > is elapsed. Do we know suspend/resume works correctly on nightly? Should still work. You can run one of the basic tests in drv_suspend to check, or run the underlying cmd used by the igt helper library. Could very well be that the bios on your machine doesn't support autoresume for some reasons, so manually waking up is useful to test. >>> +}; >>> + >>> +struct workaround { >>> + const char *reg_name; >>> + uint32_t address; >>> +}; >>> + >>> +static struct workaround bdw_workarounds[] = >>> +{ >>> + { "GEN8_ROW_CHICKEN", GEN8_ROW_CHICKEN }, >>> + { "GEN7_ROW_CHICKEN2", GEN7_ROW_CHICKEN2 }, >>> + { "HALF_SLICE_CHICKEN3", HALF_SLICE_CHICKEN3 }, >>> + { "GEN7_HALF_SLICE_CHICKEN1", GEN7_HALF_SLICE_CHICKEN1 }, >>> + { "COMMON_SLICE_CHICKEN2", COMMON_SLICE_CHICKEN2 }, >>> + { "HDC_CHICKEN0", HDC_CHICKEN0 }, >>> + { "GEN7_CACHE_MODE_1", GEN7_CACHE_MODE_1 }, >>> + { "GEN7_GT_MODE", GEN7_GT_MODE }, >>> + { "GAMTARBMODE", GAMTARBMODE }, >>> + { "_3D_CHICKEN3", _3D_CHICKEN3 }, >>> + { "GAM_ECOCHK", GAM_ECOCHK }, >>> + { "CHICKEN_PAR1_1", CHICKEN_PAR1_1 }, >>> + { "GEN7_FF_THREAD_MODE", GEN7_FF_THREAD_MODE }, >>> + { "GEN6_RC_SLEEP_PSMI_CONTROL", GEN6_RC_SLEEP_PSMI_CONTROL }, >>> + { "GEN8_UCGCTL6", GEN8_UCGCTL6 }, >>> + { "NULL", 0xFFFF }, >>> +}; >> >> >> Crazy idea I've just had to validate that all the w/a table here is >> up-to-date with the one in the kernel: >> >> - We create a special WA_REG macro in the kernel which we use to wrap all >> registers used in workarounds at the specific use-site (i.e. not in the >> header). So >> >> I951_WRITE(WA_REG(GEN8_ROW_CHICKEN), ....); >> >> - That macro then adds the register to a table which we can dump through >> debugs with a file called intel_wa_registers. This happens at runtime. >> This is important since a static list over all platforms might included >> registers which hang some platforms when we read them. >> >> - A special subtest in this test here compares the kernel-provided list >> with the one supplied here and makes sure that all the w/a in the >> kernel >> list are in the test list, too. Or we just ditch the test list here >> completely, but that might not work for special cases where we only >> need >> to check some masks ... >> >> Opinions on this? Would this help with maintaining this testcase and >> ensuring that it is always up-to-date with the kernel w/a list? I really >> want to make sure we get this right, there's been way too many cases where >> w/a settings have been lost over resume, runtime pm, ctx switches ... >> > I will change the implementation to use this macro. > so in this case the table is updated before each use case (reset, > suspend/resume, module reload etc)? Is it not sufficient to capture the > state at the beginning? my understanding is the wa state should really stay > the same and we compare the current state (eg after reset) to the one at the > beginning rather than the state before reset. Yeah, just grabbing the wa register list once from debugfs in an igt_fixture block is good enough. > I think it is easier to maintain if we completely remove the workaround list > from igt itself, based on hardware macro can populate only those workarounds > that are applicable but you mentioned that may not work for special cases, > could you elaborate about these cases? Some w/a are set in registers which have other stuff that changes at runtime, iirc some of the ring-related registers are set in RING_CTL. So for those we'd need a mask to make sure we exclude the bits that vary. But we can solve that problem once we have it, your current list doesn't have any such special case. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-08-08 17:00 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-08-08 9:54 [RFC 0/2] Add test to verify BDW workarounds arun.siluvery 2014-08-08 9:54 ` [RFC 1/2] tools/null_state_render: Add BDW workarounds to golden render state arun.siluvery 2014-08-08 9:54 ` [RFC 2/2] igt/gem_workarounds: igt to test workaround registers arun.siluvery 2014-08-08 14:12 ` Daniel Vetter 2014-08-08 16:39 ` Siluvery, Arun 2014-08-08 17:00 ` Daniel Vetter
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.