Re: Usage of _PAGE_PCD et al in i915 driver

[Juergen Gross <jgross@suse.com>]

On 08/13/2014 05:07 PM, Jesse Barnes wrote:
> On Fri, 8 Aug 2014 15:14:15 +0200
> Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
>
>> Adding relevant mailing lists.
>>
>> On Fri, Aug 8, 2014 at 1:23 PM, Juergen Gross <jgross@suse.com> wrote:
>>> I'm just about to create a patch for full PAT support in the Linux
>>> kernel, including Xen. For this purpose I introduce a translation
>>> between cache modes and pte bits.
>>>
>>> Scanning the kernel sources for usage of the cache mode bits in the
>>> pte I discovered  drivers/gpu/drm/i915/i915_gem_gtt.h is using
>>> _PAGE_PCD, _PAGE_PWT and _PAGE_PAT. I think those defines are used
>>> to create ptes not for usage by the main processor, but for the
>>> graphics processor. Is this true? In this case I'd suggest to define
>>> i915-specific macros instead of using the x86 ones.
>>
>> Yeah, those are gpu specific PAT tables, but the hw engineers
>> specifically designed this to match, and we've tried to follow the cpu
>> side to match it. Especially in the future that will be somewhat
>> important, since we want to fully share the entire address space
>> between cpu and gpu on the next platform. Jesse is working on that.
>
> Right, we have an x86 compatible MMU in the GPU itself, so re-using the
> defines makes sense.  I suppose with your work you'll move them and
> make them a bit more opaque?  If so, we'll still want a way to get at
> them directly, or access your mapping functions for generating PTE bits
> for the GPU MMU.

Using the mapping functions I'm introducing should work, if the MMU has
an x86 compatible MSR_IA32_CR_PAT which is configured the same way as
on the x86 processor (be aware that Xen is using another MSR_IA32_CR_PAT
setting as the Linux kernel).

Juergen