From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrzej Hajda Subject: Re: [PATCH 2/2] drm/exynos: mipi-dsi: consider non-continuous clock mode Date: Mon, 18 Aug 2014 12:13:04 +0200 Message-ID: <53F1D1B0.4030208@samsung.com> References: <1408349495-25568-1-git-send-email-inki.dae@samsung.com> <1408349495-25568-3-git-send-email-inki.dae@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) by gabe.freedesktop.org (Postfix) with ESMTP id 10E4D88007 for ; Mon, 18 Aug 2014 03:13:15 -0700 (PDT) Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout1.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NAH00DLDZ1TAG90@mailout1.w1.samsung.com> for dri-devel@lists.freedesktop.org; Mon, 18 Aug 2014 11:13:05 +0100 (BST) In-reply-to: <1408349495-25568-3-git-send-email-inki.dae@samsung.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Inki Dae , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org On 08/18/2014 10:11 AM, Inki Dae wrote: > This patch adds non-continuous clock mode support > > Clock mode on Clock Lane is continuous clock by default. > So if we want to transmit data in non-continuous clock mode > to reduce power consumption, then host driver should set > DSIM_CLKLANE_STOP bit. In this case, host controller turns off > HS clock between high speed transmissions. > > For this, this patch adds a new bit, DSIM_CLKLANE_STOP, and makes > the host driver set this bit only in case that dsi->mode_flags has > MIPI_DSI_CLOCK_NON_CONTINUOUS flag. > > Signed-off-by: Inki Dae Acked-by: Andrzej Hajda -- Regards Andrzej > --- > drivers/gpu/drm/exynos/exynos_drm_dsi.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c > index 442aa2d..2d47290 100644 > --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c > +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c > @@ -114,6 +114,8 @@ > #define DSIM_SYNC_INFORM (1 << 27) > #define DSIM_EOT_DISABLE (1 << 28) > #define DSIM_MFLUSH_VS (1 << 29) > +/* This flag is valid only for exynos3250/3472/4415/5260/5430 */ > +#define DSIM_CLKLANE_STOP (1 << 30) > > /* DSIM_ESCMODE */ > #define DSIM_TX_TRIGGER_RST (1 << 4) > @@ -262,6 +264,7 @@ struct exynos_dsi_driver_data { > unsigned int plltmr_reg; > > unsigned int has_freqband:1; > + unsigned int has_clklane_stop:1; > }; > > struct exynos_dsi { > @@ -304,6 +307,7 @@ struct exynos_dsi { > static struct exynos_dsi_driver_data exynos4_dsi_driver_data = { > .plltmr_reg = 0x50, > .has_freqband = 1, > + .has_clklane_stop = 1, > }; > > static struct exynos_dsi_driver_data exynos5_dsi_driver_data = { > @@ -569,6 +573,7 @@ static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) > > static int exynos_dsi_init_link(struct exynos_dsi *dsi) > { > + struct exynos_dsi_driver_data *driver_data = dsi->driver_data; > int timeout; > u32 reg; > u32 lanes_mask; > @@ -650,6 +655,20 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi) > reg |= DSIM_LANE_EN(lanes_mask); > writel(reg, dsi->reg_base + DSIM_CONFIG_REG); > > + /* > + * Use non-continuous clock mode if the periparal wants and > + * host controller supports > + * > + * In non-continous clock mode, host controller will turn off > + * the HS clock between high-speed transmissions to reduce > + * power consumption. > + */ > + if (driver_data->has_clklane_stop && > + dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { > + reg |= DSIM_CLKLANE_STOP; > + writel(reg, dsi->reg_base + DSIM_CONFIG_REG); > + } > + > /* Check clock and data lane state are stop state */ > timeout = 100; > do {