From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by yocto-www.yoctoproject.org (Postfix, from userid 118) id 287DBE007F1; Mon, 18 Aug 2014 05:57:19 -0700 (PDT) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on yocto-www.yoctoproject.org X-Spam-Level: X-Spam-Status: No, score=0.1 required=5.0 tests=BAYES_00,DEAR_SOMETHING, FROM_12LTRDOM,HTML_MESSAGE autolearn=no version=3.3.1 X-Spam-HAM-Report: * 2.0 DEAR_SOMETHING BODY: Contains 'Dear (something)' * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] * 0.0 HTML_MESSAGE BODY: HTML included in message * 0.0 FROM_12LTRDOM From a 12-letter domain X-Greylist: delayed 402 seconds by postgrey-1.32 at yocto-www; Mon, 18 Aug 2014 05:57:07 PDT Received: from sip2-98.nexcess.net (iwavesystems.com [207.32.180.10]) by yocto-www.yoctoproject.org (Postfix) with ESMTP id DA372E007EE for ; Mon, 18 Aug 2014 05:57:07 -0700 (PDT) Received: (qmail 21202 invoked by uid 108); 18 Aug 2014 08:50:24 -0400 Received: from unknown (HELO ?192.168.2.66?) (115.119.206.104) by sip2-98.nexcess.net with SMTP; 18 Aug 2014 08:50:24 -0400 Message-ID: <53F1F68F.9050705@iwavesystems.com> Date: Mon, 18 Aug 2014 18:20:23 +0530 From: ansaris User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: meta-freescale@yoctoproject.org Subject: i.MX6 - LDO Bypass anatop regulator in Linux 3.10.17_1.0.0-GA release X-BeenThere: meta-freescale@yoctoproject.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Usage and development list for the meta-fsl-* layers List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Aug 2014 12:57:19 -0000 Content-Type: multipart/alternative; boundary="------------090604090101060904020600" --------------090604090101060904020600 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Dear sir/madam, We are using imx6Q sabresd platform for our development with Linux 3.10.17_1.0.0-GA BSP. http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.0.35_4.1.0&id=868d21a7fce9dc90808837e06b0d5e71e38b3b1b In above link shows that, the anatop "reg_pu" value is set to 0x1F which is linux-3.0.35 kernel. @@ -81,6 +101,21 @@ void mx6_cpu_regulator_init(void) regulator_set_voltage(cpu_regulator, cpu_op_tbl[0].cpu_voltage, cpu_op_tbl[0].cpu_voltage); + if (enable_ldo_mode == LDO_MODE_BYPASSED) { + /*digital bypass VDDPU/VDDSOC/VDDARM*/ + reg = __raw_readl(ANADIG_REG_CORE); + reg &= ~BM_ANADIG_REG_CORE_REG0_TRG; + reg |= BF_ANADIG_REG_CORE_REG0_TRG(0x1f); + reg &= ~BM_ANADIG_REG_CORE_REG1_TRG; + reg |= BF_ANADIG_REG_CORE_REG1_TRG(0x1f); + reg &= ~BM_ANADIG_REG_CORE_REG2_TRG; + reg |= BF_ANADIG_REG_CORE_REG2_TRG(0x1f); + __raw_writel(reg, ANADIG_REG_CORE); + /* Mask the ANATOP brown out interrupt in the GPC. */ + reg = __raw_readl(gpc_base + 0x14); + reg |= 0x80000000; + __raw_writel(reg, gpc_base + 0x14); + } clk_set_rate(cpu_clk, cpu_op_tbl[0].cpu_rate); But with reference of Linux 3.10.17_1.0.0-GA BSP, During the LDO bypass the "reg_pu" value is not set to 0x1F as mentioned below. Please clarify. file:u-boot-imx/arch/arm/cpu/armv7/mx6/soc.c void set_anatop_bypass(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 reg = readl(&anatop->reg_core); /* bypass VDDARM/VDDSOC */ reg = reg | (0x1F << 18) | 0x1F;<-- PMU_REG_CORE's reg_arm & reg_soc values are set to 0x1F writel(reg, &anatop->reg_core); } Thank you, Regards, Ansari --------------090604090101060904020600 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Dear sir/madam,

We are using imx6Q sabresd platform for our development with Linux
3.10.17_1.0.0-GA BSP.

http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.0.35_4.1.0&id=868d21a7fce9dc90808837e06b0d5e71e38b3b1b
In above link shows that, the anatop "reg_pu" value is set to 0x1F which is linux-3.0.35 kernel.
@@ -81,6 +101,21 @@ void mx6_cpu_regulator_init(void)
regulator_set_voltage(cpu_regulator,
cpu_op_tbl[0].cpu_voltage,
cpu_op_tbl[0].cpu_voltage);
+ if (enable_ldo_mode == LDO_MODE_BYPASSED) {
+ /*digital bypass VDDPU/VDDSOC/VDDARM*/
+ reg = __raw_readl(ANADIG_REG_CORE);
+ reg &= ~BM_ANADIG_REG_CORE_REG0_TRG;
+ reg |= BF_ANADIG_REG_CORE_REG0_TRG(0x1f);
+ reg &= ~BM_ANADIG_REG_CORE_REG1_TRG;
+ reg |= BF_ANADIG_REG_CORE_REG1_TRG(0x1f);
+ reg &= ~BM_ANADIG_REG_CORE_REG2_TRG;
+ reg |= BF_ANADIG_REG_CORE_REG2_TRG(0x1f);
+ __raw_writel(reg, ANADIG_REG_CORE);
+ /* Mask the ANATOP brown out interrupt in the GPC. */
+ reg = __raw_readl(gpc_base + 0x14);
+ reg |= 0x80000000;
+ __raw_writel(reg, gpc_base + 0x14);
+ }
clk_set_rate(cpu_clk, cpu_op_tbl[0].cpu_rate);
But with reference of Linux 3.10.17_1.0.0-GA BSP, During the LDO bypass the "reg_pu" value is not set to 0x1F as mentioned below. Please clarify.
file:u-boot-imx/arch/arm/cpu/armv7/mx6/soc.c
void set_anatop_bypass(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
u32 reg = readl(&anatop->reg_core);
/* bypass VDDARM/VDDSOC */
reg = reg | (0x1F << 18) | 0x1F;  <-- PMU_REG_CORE's reg_arm & reg_soc values are set to 0x1F
 writel(reg, &anatop->reg_core);
}

Thank you,
Regards,
Ansari --------------090604090101060904020600--