diff for duplicates of <53F21156.70400@opensource.altera.com> diff --git a/a/1.txt b/N1/1.txt index 9769a8a..1a3d4f4 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ On 08/17/2014 07:50 PM, Rob Herring wrote: -> On 07/30/2014 01:22 PM, tthayer at opensource.altera.com wrote: +> On 07/30/2014 01:22 PM, tthayer@opensource.altera.com wrote: >> From: Thor Thayer <tthayer@opensource.altera.com> >> >> Add the Altera SDRAM controller bindings and device tree changes to the Altera SoC project. @@ -43,7 +43,7 @@ On 08/17/2014 07:50 PM, Rob Herring wrote: >> +- reg : Should contain 1 register range(address and length) >> + >> +Example: ->> + sdr at 0xffc25000 { +>> + sdr@0xffc25000 { >> + compatible = "altr,sdr"; >> + reg = <0xffc25000 0x1000>; >> + }; @@ -55,11 +55,11 @@ On 08/17/2014 07:50 PM, Rob Herring wrote: >> }; >> }; >> ->> + sdr at 0xffc25000 { +>> + sdr@0xffc25000 { >> + compatible = "altr,sdr"; >> + reg = <0xffc25000 0x1000>; >> + ->> + sdramedac at 0 { +>> + sdramedac@0 { >> + compatible = "altr,sdram-edac"; >> + interrupts = <0 39 4>; >> + }; diff --git a/a/content_digest b/N1/content_digest index d6ea88f..89499c5 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,15 +1,35 @@ "ref\01406744573-609-1-git-send-email-tthayer@opensource.altera.com\0" "ref\01406744573-609-4-git-send-email-tthayer@opensource.altera.com\0" "ref\053F14DC2.70000@gmail.com\0" - "From\0tthayer@opensource.altera.com (Thor Thayer)\0" - "Subject\0[PATCHv9 3/3] arm: dts: Add Altera SDRAM controller bindings\0" + "From\0Thor Thayer <tthayer@opensource.altera.com>\0" + "Subject\0Re: [PATCHv9 3/3] arm: dts: Add Altera SDRAM controller bindings\0" "Date\0Mon, 18 Aug 2014 09:44:38 -0500\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Rob Herring <robherring2@gmail.com>" + pawel.moll@arm.com + mark.rutland@arm.com + ijc+devicetree@hellion.org.uk + galak@codeaurora.org + rob@landley.net + linux@arm.linux.org.uk + atull@altera.com + delicious.quinoa@gmail.com + dinguyen@altera.com + dougthompson@xmission.com + grant.likely@linaro.org + bp@alien8.de + sameo@linux.intel.com + " lee.jones@linaro.org\0" + "Cc\0devicetree@vger.kernel.org" + linux-doc@vger.kernel.org + linux-edac@vger.kernel.org + linux-kernel@vger.kernel.org + linux-arm-kernel@lists.infradead.org + " tthayer.linux@gmail.com\0" "\00:1\0" "b\0" "\n" "On 08/17/2014 07:50 PM, Rob Herring wrote:\n" - "> On 07/30/2014 01:22 PM, tthayer at opensource.altera.com wrote:\n" + "> On 07/30/2014 01:22 PM, tthayer@opensource.altera.com wrote:\n" ">> From: Thor Thayer <tthayer@opensource.altera.com>\n" ">>\n" ">> Add the Altera SDRAM controller bindings and device tree changes to the Altera SoC project.\n" @@ -52,7 +72,7 @@ ">> +- reg : Should contain 1 register range(address and length)\n" ">> +\n" ">> +Example:\n" - ">> +\tsdr at 0xffc25000 {\n" + ">> +\tsdr@0xffc25000 {\n" ">> +\t\tcompatible = \"altr,sdr\";\n" ">> +\t\treg = <0xffc25000 0x1000>;\n" ">> +\t};\n" @@ -64,11 +84,11 @@ ">> \t\t\t};\n" ">> \t\t};\n" ">> \n" - ">> +\t\tsdr at 0xffc25000 {\n" + ">> +\t\tsdr@0xffc25000 {\n" ">> +\t\t\tcompatible = \"altr,sdr\";\n" ">> +\t\t\treg = <0xffc25000 0x1000>;\n" ">> +\n" - ">> +\t\t\tsdramedac at 0 {\n" + ">> +\t\t\tsdramedac@0 {\n" ">> +\t\t\t\tcompatible = \"altr,sdram-edac\";\n" ">> +\t\t\t\tinterrupts = <0 39 4>;\n" ">> +\t\t\t};\n" @@ -89,4 +109,4 @@ "\n" Thor -eb0cfaac7b8898ce2a65a41aca9da8125dba72b368532543268af65d45a54d34 +02df254f5e97abd56bdc91dea136dfab924c326c6c7db66d97382d4a894f80a0
diff --git a/a/1.txt b/N2/1.txt index 9769a8a..1a3d4f4 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,6 +1,6 @@ On 08/17/2014 07:50 PM, Rob Herring wrote: -> On 07/30/2014 01:22 PM, tthayer at opensource.altera.com wrote: +> On 07/30/2014 01:22 PM, tthayer@opensource.altera.com wrote: >> From: Thor Thayer <tthayer@opensource.altera.com> >> >> Add the Altera SDRAM controller bindings and device tree changes to the Altera SoC project. @@ -43,7 +43,7 @@ On 08/17/2014 07:50 PM, Rob Herring wrote: >> +- reg : Should contain 1 register range(address and length) >> + >> +Example: ->> + sdr at 0xffc25000 { +>> + sdr@0xffc25000 { >> + compatible = "altr,sdr"; >> + reg = <0xffc25000 0x1000>; >> + }; @@ -55,11 +55,11 @@ On 08/17/2014 07:50 PM, Rob Herring wrote: >> }; >> }; >> ->> + sdr at 0xffc25000 { +>> + sdr@0xffc25000 { >> + compatible = "altr,sdr"; >> + reg = <0xffc25000 0x1000>; >> + ->> + sdramedac at 0 { +>> + sdramedac@0 { >> + compatible = "altr,sdram-edac"; >> + interrupts = <0 39 4>; >> + }; diff --git a/a/content_digest b/N2/content_digest index d6ea88f..c681be0 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,15 +1,35 @@ "ref\01406744573-609-1-git-send-email-tthayer@opensource.altera.com\0" "ref\01406744573-609-4-git-send-email-tthayer@opensource.altera.com\0" "ref\053F14DC2.70000@gmail.com\0" - "From\0tthayer@opensource.altera.com (Thor Thayer)\0" - "Subject\0[PATCHv9 3/3] arm: dts: Add Altera SDRAM controller bindings\0" + "From\0Thor Thayer <tthayer@opensource.altera.com>\0" + "Subject\0Re: [PATCHv9 3/3] arm: dts: Add Altera SDRAM controller bindings\0" "Date\0Mon, 18 Aug 2014 09:44:38 -0500\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Rob Herring <robherring2@gmail.com>" + <pawel.moll@arm.com> + <mark.rutland@arm.com> + <ijc+devicetree@hellion.org.uk> + <galak@codeaurora.org> + <rob@landley.net> + <linux@arm.linux.org.uk> + <atull@altera.com> + <delicious.quinoa@gmail.com> + <dinguyen@altera.com> + <dougthompson@xmission.com> + <grant.likely@linaro.org> + <bp@alien8.de> + <sameo@linux.intel.com> + " <lee.jones@linaro.org>\0" + "Cc\0<devicetree@vger.kernel.org>" + <linux-doc@vger.kernel.org> + <linux-edac@vger.kernel.org> + <linux-kernel@vger.kernel.org> + <linux-arm-kernel@lists.infradead.org> + " <tthayer.linux@gmail.com>\0" "\00:1\0" "b\0" "\n" "On 08/17/2014 07:50 PM, Rob Herring wrote:\n" - "> On 07/30/2014 01:22 PM, tthayer at opensource.altera.com wrote:\n" + "> On 07/30/2014 01:22 PM, tthayer@opensource.altera.com wrote:\n" ">> From: Thor Thayer <tthayer@opensource.altera.com>\n" ">>\n" ">> Add the Altera SDRAM controller bindings and device tree changes to the Altera SoC project.\n" @@ -52,7 +72,7 @@ ">> +- reg : Should contain 1 register range(address and length)\n" ">> +\n" ">> +Example:\n" - ">> +\tsdr at 0xffc25000 {\n" + ">> +\tsdr@0xffc25000 {\n" ">> +\t\tcompatible = \"altr,sdr\";\n" ">> +\t\treg = <0xffc25000 0x1000>;\n" ">> +\t};\n" @@ -64,11 +84,11 @@ ">> \t\t\t};\n" ">> \t\t};\n" ">> \n" - ">> +\t\tsdr at 0xffc25000 {\n" + ">> +\t\tsdr@0xffc25000 {\n" ">> +\t\t\tcompatible = \"altr,sdr\";\n" ">> +\t\t\treg = <0xffc25000 0x1000>;\n" ">> +\n" - ">> +\t\t\tsdramedac at 0 {\n" + ">> +\t\t\tsdramedac@0 {\n" ">> +\t\t\t\tcompatible = \"altr,sdram-edac\";\n" ">> +\t\t\t\tinterrupts = <0 39 4>;\n" ">> +\t\t\t};\n" @@ -89,4 +109,4 @@ "\n" Thor -eb0cfaac7b8898ce2a65a41aca9da8125dba72b368532543268af65d45a54d34 +d240c3e0c3c00162c0e56db11f87f80eb7722c5220ac92401dabcabc1812cbe3
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