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Date: Wed, 20 Aug 2014 09:05:59 +0530
From: Prabhakar Kushwaha <prabhakar@freescale.com>
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To: Scott Wood <scottwood@freescale.com>, Aaron Sierra <asierra@xes-inc.com>
Subject: Re: [PATCH 2/2] fsl_ifc: Support all 8 IFC chip selects
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On 8/20/2014 5:38 AM, Scott Wood wrote:
> On Fri, 2014-08-15 at 16:07 -0500, Aaron Sierra wrote:
>> Freescale's QorIQ T Series processors support 8 IFC chip selects
>> within a memory map backward compatible with previous P Series
>> processors which supported only 4 chip selects.
>>
>> Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
>> ---
>>   include/linux/fsl_ifc.h | 10 +++++-----
>>   1 file changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h
>> index 84d60cb..62762ff 100644
>> --- a/include/linux/fsl_ifc.h
>> +++ b/include/linux/fsl_ifc.h
>> @@ -29,7 +29,7 @@
>>   #include <linux/of_platform.h>
>>   #include <linux/interrupt.h>
>>   
>> -#define FSL_IFC_BANK_COUNT 4
>> +#define FSL_IFC_BANK_COUNT 8
> First please modify fsl_ifc_nand.c to limit itself to the number of
> banks it dynamically determines are present based on the IFC version.
>
>

Number of available bank/chip select are defined by SoC and it is 
independent of SoC.
It should be fix in following way

Option 1:
u-boot:  fix device tree with number of available chip select. It may 
require IFC binding change
Linux: Read device tree and determine the Chip Selects

or

Option 2:
Make it static because any way IFC NAND driver polls to 
FSL_IFC_BANK_COUNT to know NAND flash chip select. This patch is doing same.

Regards,
Prabhakar