From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58058) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XKOCq-0006Wn-09 for qemu-devel@nongnu.org; Thu, 21 Aug 2014 04:58:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XKOCk-0000AE-Ht for qemu-devel@nongnu.org; Thu, 21 Aug 2014 04:58:51 -0400 Received: from mail-we0-x234.google.com ([2a00:1450:400c:c03::234]:34543) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XKOCk-00009w-Ao for qemu-devel@nongnu.org; Thu, 21 Aug 2014 04:58:46 -0400 Received: by mail-we0-f180.google.com with SMTP id w61so8993868wes.39 for ; Thu, 21 Aug 2014 01:58:44 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <53F5B4C0.1080106@redhat.com> Date: Thu, 21 Aug 2014 10:58:40 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1408609864-16156-1-git-send-email-arei.gonglei@huawei.com> In-Reply-To: <1408609864-16156-1-git-send-email-arei.gonglei@huawei.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] pcie: Fix incorrect write to device ctl2 register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: arei.gonglei@huawei.com, qemu-devel@nongnu.org Cc: knut.omang@oracle.com, mst@redhat.com, weidong.huang@huawei.com, marcel.a@redhat.com Il 21/08/2014 10:31, arei.gonglei@huawei.com ha scritto: > +++ b/hw/pci/pcie.c > @@ -504,7 +504,7 @@ void pcie_cap_ari_init(PCIDevice *dev) > uint32_t pos = dev->exp.exp_cap; > pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2, > PCI_EXP_DEVCAP2_ARI); > - pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2, > + pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCTL2, > PCI_EXP_DEVCTL2_ARI); > } > IIUC the code is correct, it means that the bit can be written in devctl2. You don't want to set it, the firmware or OS can do it if they understand ARI. Paolo