[U-Boot] enabling ecc on P2041 and QoreIQ familly not valid for memory >= 4GB

[Benoit Sansoni <Benoit.Sansoni@kontron.com>]

Hi York,

Sorry for the delay. I was in holidays. I am back at work today.
Yes I have tried the other method that you proposed.
It works perfectly and It seems that this method initialized the ECC in 
a faster manner.

I faced a stability issue during ddr initialization. To resolve it I 
deactivate the autocalibration as recommended in the erratum num A-003474.
So for me the u-boot release that I am currently using is u-boot-2012.10 
and in the file u-boot-2012.10/arch/powerpc/cpu/mpc85xx/ddr-gen3.c I 
modified it
depending my ddr ram timing :

     out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
     out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
     out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
     /*dataT = fsl_dbg_timing();*/
     dataT = 0x9;
     out_be32(&ddr->timing_cfg_2, (regs->timing_cfg_2 & 0xf07fffff) | 
(dataT<<23));
     out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
     out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
     out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
     out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
     out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
     out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
     out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
     out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
     out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
     out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
     out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
     out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
     out_be32(&ddr->init_addr, regs->ddr_init_addr);
     out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);

So for me the timing_cfg_2 must be set at a deterministic value to avoid 
stability issue when the CONFIG_SYS_FSL_ERRATUM_DDR_A003474 flag is set.

Many thanks
Benoit


On 08/12/2014 08:07 PM, York Sun wrote:
> On 07/23/2014 11:56 PM, Benoit Sansoni wrote:
>> York,
>>
>> I am going to check out the method that you talk about.
>> For now the fix allow me to boot our board with 8GB it is a good step
>> for me.
>>
>> Thanks
>> Benoit
>>
>> On 07/23/2014 06:32 PM, York Sun wrote:
>>> Benoit,
>>>
>>> If your interest is in initializing DDR for ECC, you don't have use
>>> dma_meminit(). There is a better and faster way to do so. All Freescale modern
>>> DDR controllers support this feature. All you have to do is to define these macros
>>>
>>> CONFIG_DDR_ECC
>>> CONFIG_ECC_INIT_VIA_DDRCONTROLLER
>>> CONFIG_MEM_INIT_VALUE
>>>
>>> There are plenty of example for you to follow.
>>>
>>> But again, we should fix the DMA function anyway.
>>>
> Benoit,
>
> Have you tried my suggestion?
>
> York
>
>
>


-- 
Benoit SANSONI
Software Engineer
Kontron
150 rue Marcelin Berthelot | BP 244 - ZI Toulon-Est | 83078 Toulon Cedex 9 | France
P: +33 (0)4 98 16 33 68
benoit.sansoni at kontron.com