From: Arnout Vandecappelle <arnout@mind.be>
To: Laxman Dewangan <ldewangan@nvidia.com>,
Samuel Ortiz <sameo@linux.intel.com>,
Lee Jones <lee.jones@linaro.org>, Mark Brown <broonie@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: David Brown <davidb@codeaurora.org>
Subject: Re: [PATCH v2] tps65910: Work around silicon erratum SWCZ010
Date: Tue, 26 Aug 2014 18:21:18 +0200 [thread overview]
Message-ID: <53FCB3FE.2050308@mind.be> (raw)
In-Reply-To: <53FC5DF0.2040205@nvidia.com>
On 08/26/14 12:14, Laxman Dewangan wrote:
> Because this patch is dropped from Mark's tree, here is opportunity to revisit
> patch.
>
> On Friday 22 August 2014 09:00 PM, Arnout Vandecappelle (Essensium/Mind) wrote:
>> From http://www.ti.com/lit/pdf/SWCZ010 :
>>
>>
>> Workaround:
>> Repeat I2C access.
>
>> A simpler workaround is to make a dummy transfer just before the first
>> access to the tps65910 chip. This can be done unconditionally.
>> >id = chip_id;
>> + /* Work around silicon erratum SWCZ010: the tps65910 may miss the
>> + * first I2C transfer. So issue a dummy transfer before the first
>> + * real transfer.
>> + */
>> + i2c_master_send(i2c, "", 1);
>
> I think dummy read is more safe operation than dummy write.
> Dummy write can create the write on any register which can damage the critical
> settings or it may be possible that it will be incomplete calls. Datasheet has
> not been explained this clearly.
We're just sending the register address 0 of the SMBus transfer, without an
actual read/write request. If we do an i2c_master_recv, it's not a valid SMBus
transfer so we're equally unsure about how the chip will react to that.
But if you like, I can check how the chip reacts to it - most likely it'll just
ignore it, possibly it won't even ack it.
Regards,
Arnout
--
Arnout Vandecappelle arnout at mind be
Senior Embedded Software Architect +32-16-286500
Essensium/Mind http://www.mind.be
G.Geenslaan 9, 3001 Leuven, Belgium BE 872 984 063 RPR Leuven
LinkedIn profile: http://www.linkedin.com/in/arnoutvandecappelle
GPG fingerprint: 7CB5 E4CC 6C2E EFD4 6E3D A754 F963 ECAB 2450 2F1F
next prev parent reply other threads:[~2014-08-26 16:21 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-22 12:14 [PATCH] tps65910: Work around silicon erratum SWCZ010 Arnout Vandecappelle (Essensium/Mind)
2014-08-22 13:46 ` Laxman Dewangan
2014-08-22 14:01 ` Arnout Vandecappelle
2014-08-22 15:30 ` [PATCH v2] " Arnout Vandecappelle (Essensium/Mind)
2014-08-22 21:12 ` Mark Brown
2014-08-26 9:25 ` Lee Jones
2014-08-26 9:46 ` Mark Brown
2014-08-26 10:07 ` Arnout Vandecappelle
2014-08-26 10:14 ` Laxman Dewangan
2014-08-26 16:21 ` Arnout Vandecappelle [this message]
2014-08-29 7:31 ` Lee Jones
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